EP20K400FI672-3N vs EP20K400FI672-2N Comparaison
Comparaison détaillée côte à côte de EP20K400FI672-3N par Altera et EP20K400FI672-2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400FI672-3N | EP20K400FI672-2N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Unknown | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $188,75 |
| Device Type | CMOS loadable programmable logic device | — |
| Product Family | APEX 20K | — |
| Series | EP20K400 | — |
| Propagation Delay | 3.6 ns | 3.1 ns |
| Fréquence d'horloge maximale | 833 MHz | — |
| User I/O Count | 502 | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | 0.22 µm CMOS |
| Boîtier | S-PBGA-B672 | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Terminal Count | 672 terminals | — |
| Terminal Pitch | 1.000 mm | 1.0 mm |
| Type de montage | Surface mount | Surface Mount |
| Logic Capacity | [DATA_NEEDED: logic capacity] | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| Statut RoHS | unknown | Compliant (lead-free) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Typical Gates | — | 400,000 |
| Logic Elements / Cells | — | 16,640 |
| Maximum User I/O | — | 488 |
| Embedded Memory Bits | — | 212,992 bits |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count per family datasheet] |
| Core Voltage | — | 2.5 V |
| Maximum Frequency | — | 200 MHz |
| Package Body Size | — | 27 x 27 mm |
| Speed Grade | — | -2 |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 °C |
| Configuration Modes | — | PS, PPS, PPA, JTAG |
| Supported I/O Standards | — | LVTTL, LVCMOS, SSTL, HSTL |