EP20K400GC655-2V vs EP20K400GI655-2 Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-2V par Altera et EP20K400GI655-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP20K400GC655-2V | EP20K400GI655-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,75 | $175,00 |
| Series | APEX-20KC | APEX 20K (EP20K400) |
| Family | APEX 20KC (1.8 V, LVDS) | — |
| Logic Elements | 16,640 | — |
| Total RAM Bits | 212,992 | — |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | 3.1 ns (typical) |
| Process Technology | CMOS, 0.18 um | — |
| LVDS Support | Yes | — |
| Boîtier | 655-CPGA (62.48 x 62.48 mm) | SPGA-655 (47 mm x 47 mm) |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Type de montage | Through-hole (CPGA) | Through-Hole / Socket |
| Speed Grade | -2 | — |
| Température de fonctionnement | [DATA_NEEDED: temperature grade] | -40C to +85C (industrial) |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Manufacturer | — | Altera Corporation |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Typical Gate Count | — | 400,000 gates |
| Logic Elements (LE) | — | 16,640 |
| Maximum User I/O | — | 496 |
| Dedicated Inputs | — | 6 |
| Number of Terminals | — | 655 |
| Nominal Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Technology | — | CMOS SRAM |
| Moisture Sensitivity Level | — | 1 (per Altera family) |
| Configuration Method | — | JTAG, Passive Serial, Passive Parallel |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+ |
| Embedded Memory | — | Embedded System Blocks (ESBs) |
| Statut du cycle de vie | — | Obsolete (legacy Altera APEX 20K family) |