EP20K400GC655-3 vs EP20K400GC655-3X Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-3 par Intel et EP20K400GC655-3X par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400GC655-3 | EP20K400GC655-3X |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $310,00 | $65,00 |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20K | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Manufacturer | Intel (formerly Altera) | Altera (now Intel FPGA) |
| Logic Elements | 16640 | — |
| Total RAM Bits | 212992 | 212,992 bits |
| Number of Gates | 400000 | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | — |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Maximum Frequency | 167 MHz (per FPGAkey) | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| Boîtier / Format | 655-BCPGA | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | — |
| Speed Grade | -3 (slowest grade in family) | -3 (fastest) |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Maximum Internal Frequency | — | 167 MHz (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| Type de montage | — | Through-Hole (CPGA, ceramic) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |