EP20K400GI655-1 vs EP20K400GC655-1X Comparaison
Comparaison détaillée côte à côte de EP20K400GI655-1 par Altera et EP20K400GC655-1X par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400GI655-1 | EP20K400GC655-1X |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $195,00 | $193,04 |
| Family | APEX 20K | — |
| Device Series | EP20K400 | — |
| Technology | CMOS, SRAM-based | CMOS |
| Logic Elements | 16640 | 16640 cells |
| Typical Gates | 400000 | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 655 | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | CPGA-655 (Ceramic Pin Grid Array) |
| JESD-30 Package Code | S-CPGA-P655 | — |
| Température de fonctionnement | -40C to +85C (Industrial) | — |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 C | — |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | — |
| Process Node | 0.18 micrometer CMOS | — |
| Statut RoHS | Compliant | unknown |
| Product Family | — | Altera APEX 20K |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Gate Count | — | 400K gates |
| Maximum System Frequency | — | 250 MHz |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V / 3.3 V |
| Number of User I/O | — | 496 |
| Number of Dedicated Inputs | — | 6 |
| Number of Terminals | — | 655 |
| Package Body Material | — | Ceramic |
| Process Technology | — | 0.22 um |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Embedded RAM Bits | — | [DATA_NEEDED: embedded RAM bits] |