EP20K600CB652C9N vs EP20K600CB652C7ES Comparaison
Comparaison détaillée côte à côte de EP20K600CB652C9N par Intel et EP20K600CB652C7ES par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CB652C9N | EP20K600CB652C7ES |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $128,00 | $195,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD (FPGA) | — |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O | 488 | 488 |
| Boîtier | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) | — |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 µm CMOS |
| Core Supply Voltage | 1.8 V | — |
| Speed Grade | C9 (~1.48 ns propagation delay) | — |
| Architecture | MultiCore LUT + embedded system memory (ESB) | — |
| On-chip Memory | Embedded system memory blocks (dual-port RAM, FIFO) | — |
| Configuration Interface | JTAG (IEEE 1149.1) and serial/PROM configuration | — |
| Température de fonctionnement | 0 C to 85 C (commercial) | 0 °C to +85 °C (commercial) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Pin/Pin Compatibility | Pin-compatible with APEX 20KE devices of same package | — |
| Toolchain | Altera/Intel Quartus II (legacy APEX support) | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| System Gates | — | 600,000 |
| Maximum System Gates | — | 1,053,840 |
| Embedded Memory Bits | — | 311,296 |
| Embedded System Blocks (ESB) | — | 26 |
| User I/O (this package) | — | 488 (652-BGA) |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | — | 1666.6 MHz |
| Propagation Delay | — | 1.6 ns |
| Package Type | — | 652-ball FineLine BGA |
| JEDEC Package Code | — | S-PBGA-B652 |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| PLLs | — | 4 |