EP20K600CB652C9N vs EP20K600CB652C7ES Comparação
Comparação detalhada lado a lado de EP20K600CB652C9N por Intel e EP20K600CB652C7ES por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP20K600CB652C9N | EP20K600CB652C7ES |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $128,00 | $195,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD (FPGA) | — |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O | 488 | 488 |
| Encapsulamento | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) | — |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 µm CMOS |
| Core Supply Voltage | 1.8 V | — |
| Speed Grade | C9 (~1.48 ns propagation delay) | — |
| Architecture | MultiCore LUT + embedded system memory (ESB) | — |
| On-chip Memory | Embedded system memory blocks (dual-port RAM, FIFO) | — |
| Configuration Interface | JTAG (IEEE 1149.1) and serial/PROM configuration | — |
| Temperatura de operação | 0 C to 85 C (commercial) | 0 °C to +85 °C (commercial) |
| Tipo de montagem | Surface Mount (BGA) | Surface Mount (BGA) |
| Pin/Pin Compatibility | Pin-compatible with APEX 20KE devices of same package | — |
| Toolchain | Altera/Intel Quartus II (legacy APEX support) | — |
| Status RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Nível MSL | [DATA_NEEDED: MSL level] | — |
| System Gates | — | 600,000 |
| Maximum System Gates | — | 1,053,840 |
| Embedded Memory Bits | — | 311,296 |
| Embedded System Blocks (ESB) | — | 26 |
| User I/O (this package) | — | 488 (652-BGA) |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | — | 1666.6 MHz |
| Propagation Delay | — | 1.6 ns |
| Package Type | — | 652-ball FineLine BGA |
| JEDEC Package Code | — | S-PBGA-B652 |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| PLLs | — | 4 |