EP20K600CB672C7 vs EP20K600CB672C8N Comparaison
Comparaison détaillée côte à côte de EP20K600CB672C7 par Altera et EP20K600CB672C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CB672C7 | EP20K600CB672C8N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $182,50 | $69,00 |
| Family | APEX 20KC | APEX-20KC |
| Device Type | FPGA / Programmable Logic Device (PLD) | — |
| Typical Gates | 600,000 | — |
| Maximum System Gates | 1,053,840 | — |
| Logic Elements | 30,960 (typical) | — |
| Embedded Memory | 311 kbits (EAB-based) | — |
| User I/Os | 488 | — |
| Boîtier | 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch) | 672-BBGA (FineLine BGA) |
| Speed Grade | C7 (commercial, 0 °C to 85 °C) | C8 |
| Propagation Delay | 1.48 ns | — |
| Process Technology | 0.15 µm all-layer copper-metal CMOS | 0.18 µm CMOS |
| Core Voltage | 2.5 V | — |
| I/O Voltage Support | 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O) | — |
| Number of PLLs | 4 | — |
| Dual-Port RAM | Yes (4.5 ns access) | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT | — |
| Température de fonctionnement | 0 °C to 85 °C (commercial) | Commercial (0C to +85C) |
| Configuration Method | EPC configuration devices / JTAG / passive serial | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Logic Elements (LEs) | — | 24,320 |
| Embedded Memory Bits | — | 311,296 |
| Maximum User I/O | — | 508 |
| Configuration Memory | — | SRAM, in-system programmable |
| Configuration Schemes | — | Passive Serial / Active Serial / JTAG (IEEE 1149.1) |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| PCI Support | — | PCI-SIG compliant 3.3 V, 33/66 MHz, 32/64-bit |
| External Memory Interface | — | DDR SDRAM, ZBT SRAM |
| Dedicated Clock Inputs | — | 16 |
| PLLs | — | On-chip with clock-doubling and phase-shift |
| LVDS Channels | — | Up to 32 |
| Type de montage | — | Surface Mount (BGA) |