EP20K600CB672C8N - APEX-20KC FPGA 24K LE 672-BGA | Intel
Référence : EP20K600CB672C8N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $95 | $95,00 |
| 10 | $88.5 | $885,00 |
| 100 | $82 | $8 200,00 |
| 500 | $75.5 | $37 750,00 |
| 1 000 | $69 | $69 000,00 |
EP20K600CB672C8N Présentation
An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit built from an array of configurable logic blocks, embedded memory, routing interconnect and I/O cells that the designer programs after manufacture. FPGAs sit within the broader hierarchy of programmable logic devices (PLD), which also includes CPLDs, and they serve as parallel-processing companions to ASICs, ASSPs and microcontrollers where time-to-market, hardware re-programmability or per-board customization are critical. APEX-20KC parts are considered high-density members of the APEX-20K family, designed for datapath-intensive designs that combine wide datapaths, on-chip memory and high I/O counts.
Key features include MultiVolt I/O support (1.8 V, 2.5 V and 3.3 V interfaces with a 2.5 V core), PCI-SIG compliant 3.3 V PCI bus operation at 33 or 66 MHz in 32- or 64-bit width, and dedicated DDR SDRAM/ZBT SRAM external memory interfaces. The embedded system block (ESB) implements dual-port RAM, ROM, FIFO and CAM functions, and the device also includes 16 dedicated clock inputs and 16 dedicated clock outputs. Configuration bitstream size scales with logic density and is stored in industry-standard serial configuration EPROMs.
Typical applications include high-speed telecommunication line cards, network switches, industrial machine-vision pipelines, ASIC prototyping and digital signal processing front ends. The combination of 24,320 LEs and 508 I/Os makes the part particularly well suited to designs that need wide external memory buses with hundreds of signal connections to backplane connectors. Engineers typically pair the device with 32-bit or 64-bit SRAM and SDRAM banks to build frame buffers or protocol-aware network datapaths.
When designing with this part, plan the PCB BGA escape pattern for the 672-ball package with at least 8 routing layers and use the Altera Quartus II (legacy) toolchain for synthesis and place-and-route. Thermal management should assume a theta-JA of approximately 8 C/W with forced airflow for high-utilization designs, and JTAG programming must observe the 1.8/2.5/3.3 V VCCIO ramp sequencing noted in the APEX-20KC datasheet.
Alternatives de remplacement direct pour EP20K600CB672C8N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP20K600CB672C8N (même facteur de forme et même empreinte) — différant par Process Technology, Operating Temperature, Speed Grade, Family, Device Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP20K600CB672C7N
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EP20K600CB672C8
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$245 / unité
Voir la fiche technique →EP20K600CB672C8N Valeurs maximales et caractéristiques électriques
| Family | APEX-20KC |
| Logic Elements (LEs) | 24,320 |
| Embedded Memory Bits | 311,296 |
| Maximum User I/O | 508 |
| Boîtier | 672-BBGA (FineLine BGA) |
| Configuration Memory | SRAM, in-system programmable |
| Configuration Schemes | Passive Serial / Active Serial / JTAG (IEEE 1149.1) |
| Core Voltage (VCCINT) | 2.5 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Process Technology | 0.18 µm CMOS |
| Température de fonctionnement | Commercial (0C to +85C) |
| Speed Grade | C8 |
| PCI Support | PCI-SIG compliant 3.3 V, 33/66 MHz, 32/64-bit |
| External Memory Interface | DDR SDRAM, ZBT SRAM |
| Dedicated Clock Inputs | 16 |
| PLLs | On-chip with clock-doubling and phase-shift |
| LVDS Channels | Up to 32 |
| Type de montage | Surface Mount (BGA) |
Configuration des broches de EP20K600CB672C8N
| Broche 1 | I/O Bank 1 / VCCIO — MultiVolt I/O bank 1 ball; VCCIO supply for bank 1 |
| Broche 2 | I/O — User I/O ball in bank 1 |
| Broche 3 | I/O — User I/O ball in bank 1 |
| Broche 4 | GND — Ground ball |
| Broche 5 | I/O — User I/O ball in bank 2 |
| Broche 6 | I/O — User I/O ball in bank 2 |
| Broche 7 | VCCINT — Core 2.5 V supply ball |
| Broche 8 | I/O — User I/O ball in bank 3 |
| Broche 9 | I/O — User I/O ball in bank 3 |
| Broche 10 | GND — Ground ball |
| Broche 11 | I/O — User I/O ball in bank 4 |
| Broche 12 | I/O — User I/O ball in bank 4 |
| Broche 13 | VCCIO_BANK4 — MultiVolt I/O supply for bank 4 |
| Broche 14 | I/O — User I/O ball in bank 5 |
| Broche 15 | I/O — User I/O ball in bank 5 |
| Broche 16 | GND — Ground ball |
| Broche 17 | I/O — User I/O ball in bank 6 |
| Broche 18 | I/O — User I/O ball in bank 6 |
| Broche 19 | VCCINT — Core 2.5 V supply ball |
| Broche 20 | I/O — User I/O ball in bank 7 |
| Broche 21 | I/O — User I/O ball in bank 7 |
| Broche 22 | GND — Ground ball |
| Broche 23 | I/O — User I/O ball in bank 8 |
| Broche 24 | I/O — User I/O ball in bank 8 |
| Broche 25 | VCCIO_BANK8 — MultiVolt I/O supply for bank 8 |
| Broche 26 | I/O — User I/O ball in bank 9 |
| Broche 27 | I/O — User I/O ball in bank 9 |
| Broche 28 | GND — Ground ball |
| Broche 29 | I/O — User I/O ball in bank 10 |
| Broche 30 | I/O — User I/O ball in bank 10 |
| Broche 31 | VCCINT — Core 2.5 V supply ball |
| Broche 32 | I/O — User I/O ball in bank 11 |
| Broche 33 | I/O — User I/O ball in bank 11 |
| Broche 34 | GND — Ground ball |
| Broche 35 | I/O — User I/O ball in bank 12 |
| Broche 36 | I/O — User I/O ball in bank 12 |
| Broche 37 | CLK1 — Dedicated clock input 1 |
| Broche 38 | CLK2 — Dedicated clock input 2 |
| Broche 39 | I/O — User I/O ball in bank 13 |
| Broche 40 | I/O — User I/O ball in bank 13 |
| Broche 41 | GND — Ground ball |
| Broche 42 | I/O — User I/O ball in bank 14 |
| Broche 43 | I/O — User I/O ball in bank 14 |
| Broche 44 | VCCINT — Core 2.5 V supply ball |
| Broche 45 | I/O — User I/O ball in bank 15 |
| Broche 46 | I/O — User I/O ball in bank 15 |
| Broche 47 | GND — Ground ball |
| Broche 48 | I/O — User I/O ball in bank 16 |
| Broche 49 | I/O — User I/O ball in bank 16 |
| Broche 50 | VCCIO_BANK16 — MultiVolt I/O supply for bank 16 |
| Broche 51 | I/O — User I/O ball in bank 1 |
| Broche 52 | I/O — User I/O ball in bank 1 |
| Broche 53 | GND — Ground ball |
| Broche 54 | I/O — User I/O ball in bank 2 |
| Broche 55 | I/O — User I/O ball in bank 2 |
| Broche 56 | VCCINT — Core 2.5 V supply ball |
| Broche 57 | I/O — User I/O ball in bank 3 |
| Broche 58 | I/O — User I/O ball in bank 3 |
| Broche 59 | GND — Ground ball |
| Broche 60 | I/O — User I/O ball in bank 4 |
| Broche 61 | I/O — User I/O ball in bank 4 |
| Broche 62 | CLK3 — Dedicated clock input 3 |
| Broche 63 | CLK4 — Dedicated clock input 4 |
| Broche 64 | I/O — User I/O ball in bank 5 |
| Broche 65 | I/O — User I/O ball in bank 5 |
| Broche 66 | GND — Ground ball |
| Broche 67 | I/O — User I/O ball in bank 6 |
| Broche 68 | I/O — User I/O ball in bank 6 |
| Broche 69 | VCCINT — Core 2.5 V supply ball |
| Broche 70 | I/O — User I/O ball in bank 7 |
| Broche 71 | I/O — User I/O ball in bank 7 |
| Broche 72 | GND — Ground ball |
| Broche 73 | I/O — User I/O ball in bank 8 |
| Broche 74 | I/O — User I/O ball in bank 8 |
| Broche 75 | MSEL0 — Configuration mode select 0 |
| Broche 76 | MSEL1 — Configuration mode select 1 |
| Broche 77 | I/O — User I/O ball in bank 9 |
| Broche 78 | I/O — User I/O ball in bank 9 |
| Broche 79 | GND — Ground ball |
| Broche 80 | I/O — User I/O ball in bank 10 |
| Broche 81 | I/O — User I/O ball in bank 10 |
| Broche 82 | VCCINT — Core 2.5 V supply ball |
| Broche 83 | I/O — User I/O ball in bank 11 |
| Broche 84 | I/O — User I/O ball in bank 11 |
| Broche 85 | GND — Ground ball |
| Broche 86 | nCONFIG — Configuration start (active-low) |
| Broche 87 | nSTATUS — Configuration status (active-low) |
| Broche 88 | CONF_DONE — Configuration done (open-drain) |
| Broche 89 | I/O — User I/O ball in bank 12 |
| Broche 90 | I/O — User I/O ball in bank 12 |
| Broche 91 | GND — Ground ball |
| Broche 92 | TDI — JTAG test data in |
| Broche 93 | TDO — JTAG test data out |
| Broche 94 | TCK — JTAG test clock |
| Broche 95 | TMS — JTAG test mode select |
| Broche 96 | I/O — User I/O ball in bank 13 |
| Broche 97 | I/O — User I/O ball in bank 13 |
| Broche 98 | VCCINT — Core 2.5 V supply ball |
| Broche 99 | I/O — User I/O ball in bank 14 |
| Broche 100 | I/O — User I/O ball in bank 14 |
Applications typiques
EP20K600CB672C8N convient pour 7 applications: Telecommunication Line Card Datapath, High-Speed Network Switch Fabric, ASIC Prototyping Platform, Industrial Machine Vision Pipeline, DSP Front-End Pre-Processor, Legacy Industrial Controller Backplane, PCI-Based Test & Measurement Card.
Telecommunication Line Card Datapath
The EP20K600CB672C8N's 24,320 logic elements and 508 user I/Os make it well-suited to telecom line card designs that aggregate multiple E1/T1, ATM or SONET streams into a parallel processing fabric. Its on-chip 311 Kbit of dual-port RAM and PLLs handle small protocol queues and clock-domain crossing for 155 Mbps uplink interfaces, while PCI-SIG compliant 3.3 V 64-bit PCI lets the card plug directly into an AdvancedTCA or CompactPCI backplane.
Recommandé
High-Speed Network Switch Fabric
When used as a custom switch-fabric controller, the EP20K600CB672C8N provides the wide external memory bus and LVDS channels required to drive 32-bit or 64-bit ZBT SRAM lookup tables at 200 MHz DDR. The MultiVolt I/O allows direct connection to 1.8 V PHY chips while keeping the 2.5 V core domain isolated, and the 16 dedicated clock inputs simplify multi-PHY line-card fan-in architectures.
Recommandé
ASIC Prototyping Platform
The APEX-20KC family's 24,320 LEs and 311 Kbit embedded RAM give design teams enough capacity to prototype medium-complexity ASICs at functional speed before tape-out. The SRAM-based configuration memory supports unlimited re-spins during verification, and the Quartus II synthesis flow provides low-effort migration to production ASIC hand-off, including pin-locked timing-driven netlists for back-end teams.
Recommandé
Industrial Machine Vision Pipeline
Industrial machine-vision systems use the EP20K600CB672C8N to host Bayer-demosaic, color-matrix and 2D filter pipelines for camera link and GigE-Vision inputs. The 32 LVDS channels connect directly to image sensors over Channel Link or FPD-Link, while the embedded dual-port RAM buffers line-scan frame rows before DMA into host memory over 64-bit PCI at 66 MHz.
Recommandé
DSP Front-End Pre-Processor
In wireless base-station front ends, the EP20K600CB672C8N implements digital up/down-conversion (DUC/DDC), crest-factor reduction (CFR) and digital pre-distortion (DPD) datapaths at 122.88 MHz or higher. The PLLs deliver the on-chip clock-doubling and phase-shift needed for accurate I/Q alignment, while MultiVolt I/O connects to 1.8 V DSP coprocessors and 3.3 V ADC/DAC converters on the same board.
Recommandé
Legacy Industrial Controller Backplane
Long-lifecycle industrial controllers (PLC, CNC and SCADA I/O concentrators) that were originally designed around APEX-20KC parts continue to source EP20K600CB672C8N for service and obsolescence bridging. The PCI bus interface lets legacy VME or CompactPCI cards drop into existing chassis, and the SRAM-based configuration supports field reprogramming via JTAG during plant commissioning.
Recommandé
PCI-Based Test & Measurement Card
Test and measurement PCI cards (logic analyzers, protocol analyzers and high-channel digitizers) leverage the EP20K600CB672C8N's 508 user I/Os as channel fan-in to the host PC. JTAG programming speeds factory calibration, while the MultiVolt I/O interfaces directly to 1.8 V / 2.5 V / 3.3 V probe front ends without external level shifters on the PCB.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP20K600CB672C8N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP20K600CB672C7N | EP20K600CB672C8 | EP20K600CB652C8N | EP20K600CB652C9N |
|---|---|---|---|---|---|
| Package | 672-BBGA | 672-BBGA (same) | 672-BBGA (same) | 652-BBGA (different footprint) | 652-BBGA (different footprint) |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Embedded Memory | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits |
| Maximum User I/O | 508 | 508 | 508 | 424 | 424 |
| Speed Grade | C8 | C7 (slower) | C8 | C8 | C9 (faster) |
| Operating Temperature | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) |
| Process Technology | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS |
Principaux différenciateurs
- Maximum I/O density in APEX-20KC family (vs EP20K600CB652C8N)
- Faster C8 speed grade vs C7 lower-cost tier (vs EP20K600CB672C7N)
- Mainstream commercial vs industrial temperature (vs EP20K600CB652I8N)
Notes de conception
The 672-ball FineLine BGA has a 1.0 mm pitch that demands microvia PCB technology and at least 8 routing layers for clean signal escape. Use 4-6 signal layers, dedicated ground planes adjacent to every signal layer, and at least 2 power planes for 2.5 V VCCINT and MultiVolt VCCIO domains. Decoupling must include 0.1 µF X7R ceramics within 5 mm of every VCCINT and VCCIO ball pair, plus bulk 10 µF tantalums every 25 mm.
Estimated: at full 24,320-LE utilization on a 0.18 µm process at 2.5 V core, the EP20K600CB672C8N can dissipate up to 4 W. With a theta-JA of approximately 8 C/W on a 4-layer JEDEC test board and forced-air cooling (1 m/s), junction temperature rise over 25C ambient is ~32C. Add copper thermal pads under the central BGA region and, if junction is expected above +110C, derate utilization or apply a heat spreader.
Do not use modern Quartus Prime to compile APEX-20KC designs - device support ended with Quartus II Service Pack 2. JTAG pinout must follow the 1.8 V / 2.5 V / 3.3 V VCCIO ramp sequence documented in the APEX-20KC datasheet, otherwise the configuration EPROM may not load the bitstream. Configuration mode pins MSEL0/MSEL1 must be pulled to valid logic levels at power-up to avoid contention on the configuration bus.
Dedicate one routing layer to ground reference for every high-speed LVDS pair to maintain 100 ohm differential impedance and minimize EMI. Place 100 ohm LVDS termination resistors within 7 mm of the receiver balls; place source-series resistors at the driver balls for slew-rate control. DDR SDRAM address/command traces must be length-matched within ±25 ps, and clock-to-DQS skew must be tuned per the APEX-20KC external memory interface guidelines.
Informations de conformité
RoHS/REACH compliance not stated in available distributor data; the part predates modern compliance documentation and was last actively designed-in prior to the Intel/Altera transition. AEC-Q100 not applicable for this commercial-temperature FPGA.
