EP20K600CF672C-7ES vs EP20K600CEF672C7 Comparaison
Comparaison détaillée côte à côte de EP20K600CF672C-7ES par Altera et EP20K600CEF672C7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF672C-7ES | EP20K600CEF672C7 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2 050,00 | $98,40 |
| Family | APEX 20KC | APEX 20KC (Enhanced Configuration) |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA / Loadable PLD |
| Maximum System Gates | 1,560,000 (typical 600K application gates) | — |
| Typical Logic Elements | 24,320 (per APEX 20KC 600K family) | — |
| Maximum User I/O | 488 | — |
| Total I/O Lines | 504 (per Microchip USA listing) | — |
| Total Inputs | 508 | — |
| Embedded System Blocks (ESBs) | 248 | — |
| Embedded RAM | 248 Kbits (dual-port) | — |
| PLLs | 4 | — |
| Propagation Delay | 1.48 ns to 1.6 ns | 1.48 ns (typ) |
| Fréquence d'horloge maximale | 1666.6 MHz | — |
| Speed Grade | -7 | — |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 µm CMOS, all-layer copper |
| Boîtier | 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA (FC-FBGA) |
| Température de fonctionnement | 0 C to 85 C (Commercial) | 0 °C to +85 °C (commercial) |
| Core Voltage | 1.8 V (typical APEX 20KC, exact value per datasheet) | — |
| Configuration Mode | EPC serial / JTAG IEEE 1149.1 | — |
| Compliance | RoHS status unknown (verify with manufacturer datasheet) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | APEX 20KC |
| Logic Elements / Cells | — | 24,320 |
| Gate Count (typical) | — | 600,000 gates |
| Maximum Operating Frequency | — | 375.94 MHz |
| User I/Os | — | 488 |
| Core Supply Voltage | — | 1.8 V |
| Package Code | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration | — | SRAM-based, serial or parallel (EPC) |
| Embedded Memory | — | EAB blocks (dual-port RAM with byte enables) |
| LVDS Support | — | True-LVDS channels integrated |
| MultiVolt I/O | — | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | — | DDR SDRAM, QDR SRAM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |