EP20K600CF672C-7ES vs EP20K600CEF672C7 比較
詳細な並列比較: EP20K600CF672C-7ES メーカー: Altera および EP20K600CEF672C7 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600CF672C-7ES | EP20K600CEF672C7 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $2,050.00 | $98.40 |
| Family | APEX 20KC | APEX 20KC (Enhanced Configuration) |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA / Loadable PLD |
| Maximum System Gates | 1,560,000 (typical 600K application gates) | — |
| Typical Logic Elements | 24,320 (per APEX 20KC 600K family) | — |
| Maximum User I/O | 488 | — |
| Total I/O Lines | 504 (per Microchip USA listing) | — |
| Total Inputs | 508 | — |
| Embedded System Blocks (ESBs) | 248 | — |
| Embedded RAM | 248 Kbits (dual-port) | — |
| PLLs | 4 | — |
| Propagation Delay | 1.48 ns to 1.6 ns | 1.48 ns (typ) |
| 最大クロック周波数 | 1666.6 MHz | — |
| Speed Grade | -7 | — |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 µm CMOS, all-layer copper |
| パッケージ | 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA (FC-FBGA) |
| 動作温度 | 0 C to 85 C (Commercial) | 0 °C to +85 °C (commercial) |
| Core Voltage | 1.8 V (typical APEX 20KC, exact value per datasheet) | — |
| Configuration Mode | EPC serial / JTAG IEEE 1149.1 | — |
| Compliance | RoHS status unknown (verify with manufacturer datasheet) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | APEX 20KC |
| Logic Elements / Cells | — | 24,320 |
| Gate Count (typical) | — | 600,000 gates |
| Maximum Operating Frequency | — | 375.94 MHz |
| User I/Os | — | 488 |
| Core Supply Voltage | — | 1.8 V |
| Package Code | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration | — | SRAM-based, serial or parallel (EPC) |
| Embedded Memory | — | EAB blocks (dual-port RAM with byte enables) |
| LVDS Support | — | True-LVDS channels integrated |
| MultiVolt I/O | — | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | — | DDR SDRAM, QDR SRAM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status] |