EP20K600CF672C7ES vs EP20K600CF672-2 Comparaison
Comparaison détaillée côte à côte de EP20K600CF672C7ES par Altera et EP20K600CF672-2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera
EP20K600CF672C7ES ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP20K600CF672C7ES | EP20K600CF672-2 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $360,00 | $680,00 |
| Series | APEX 20KC | APEX 20KC |
| Family | APEX 20K | — |
| Logic Elements / Cells | 24320 | — |
| System Gates | 600000 | — |
| Maximum User I/O | 504 | — |
| Maximum Input Lines | 508 | — |
| Number of Macrocells | 504 | — |
| Maximum Operating Frequency | 375.94 MHz (per FPGAkey listing) | — |
| Propagation Delay | 1.6 ns | — |
| Internal Reference Clock | 1666.6 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.18 um CMOS |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| Package Type | FC-FBGA | 672-ball FineLine BGA (FCBGA) |
| Pin / Ball Count | 672 | — |
| Grade Suffix | ES (engineering sample / extended screening) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | 0 C to +60 C (TJ, per Alibaba supplier listing) |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs_status] |
| Configuration Memory | SRAM-based (volatile) | — |
| Manufacturer | — | Intel / Altera |
| Device Family | — | APEX 20KC PLD |
| Gate Count (typical) | — | 600,000 gates |
| Logic Elements | — | 30,720 |
| Embedded RAM (approx.) | — | 311,232 bits |
| Speed Grade | — | -2 |
| Configuration Mode | — | Enhanced Configuration (EPC) |
| Number of PLLs | — | 4 |
| I/O Standards | — | LVTTL, LVCMOS, and others per datasheet |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Statut du cycle de vie | — | Obsolete / last-time-buy |