EP20K600CF672C8 vs EP20K600CF672C6 Comparaison
Comparaison détaillée côte à côte de EP20K600CF672C8 par Intel et EP20K600CF672C6 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF672C8 | EP20K600CF672C6 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Unknown | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $322,41 | $480,00 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | APEX-20K | — |
| User I/O Count | 508 | — |
| Logic Elements | 24,320 | — |
| Total RAM Bits | 311,296 bits | — |
| Propagation Delay | 1.48 ns | — |
| Package Pin Count | 672 balls | — |
| Supplier Device Package | 672-FBGA, 27 mm x 27 mm | — |
| Alternate Package Description | BGA-652, 45 mm x 45 mm, 1.27 mm pitch | — |
| Package Type | FBGA | — |
| Type de montage | Surface Mount | — |
| Tension d'alimentation | 1.71 V to 1.89 V | — |
| Température de fonctionnement | 0 C to 85 C | 0 °C to +85 °C (commercial) |
| Fabrication Process | 0.15 um | — |
| Statut RoHS | Non-compliant | Non-RoHS (legacy process) |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Configuration Interface | [DATA_NEEDED: configuration interface] | — |
| Maximum Core Frequency | [DATA_NEEDED: maximum core frequency] | — |
| Family | — | APEX 20KC |
| Typical Gate Count | — | 600,000 gates |
| Logic Elements (LEs) | — | 24,320 |
| Embedded System Blocks (ESBs) | — | 160 (each 2,048 bits) |
| Maximum Embedded RAM | — | 311,296 bits (311 kbit) |
| Maximum User I/O Pins | — | 508 |
| Boîtier | — | 672-ball FineLine BGA (CF672) |
| Package Body Size | — | 27 mm × 27 mm |
| Speed Grade | — | -6 (C6) |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | — | 4 |
| Process Technology | — | 0.18 µm CMOS, 6 metal layers |
| Configuration Method | — | SRAM-based, JTAG, EPC16/EPC2 |