EP20K60EFC144-2 vs EP20K60EFI144-2X Comparaison
Comparaison détaillée côte à côte de EP20K60EFC144-2 par Altera et EP20K60EFI144-2X par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K60EFC144-2 | EP20K60EFI144-2X |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,75 | $65,00 |
| Series | APEX-20K | — |
| Family | APEX-20KE (Enhanced, 1.8 V core) | — |
| Typical Gates | 60,000 | 60,000 |
| Logic Elements | 2,560 | 2,560 |
| Total RAM Bits | 32,768 | — |
| User I/O | 92 to 93 | — |
| Core Supply Voltage | 1.71 V to 1.89 V | — |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.72 ns | — |
| Process Technology | 0.18 µm CMOS | 0.22 µm CMOS |
| Boîtier | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) | — |
| Température de fonctionnement | 0 °C to +85 °C (commercial) | -40 °C to +85 °C |
| Type de montage | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | — |
| Configuration Method | Serial/Parallel passive, JTAG, EPC companion | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Family | — | APEX 20KE |
| Maximum Operating Frequency | — | 200 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V (range 1.71 V to 1.89 V) |
| Propagation Delay (tpd) | — | 2.41 ns |
| User I/O Pins | — | 93 |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 144 |
| Package Type | — | FBGA-144 (FineLine BGA, LBGA) |
| Package Code | — | LBGA |
| Terminal Form | — | Ball |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| I/O Standard Support | — | LVDS, 1.8 V I/O |
| Speed Grade | — | -2 (industrial, -2X suffix) |
| Configuration Interface | — | JTAG (IEEE 1149.1) / serial PROM / parallel PROM |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 |