EP2A25F672I6 vs EP2A25F672C9N Comparaison
Comparaison détaillée côte à côte de EP2A25F672I6 par Intel et EP2A25F672C9N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A25F672I6 | EP2A25F672C9N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $178,00 | $195,00 |
| Family | APEX II | APEX II |
| Logic Elements (typical gates) | 25,000 | — |
| Fabric Architecture | SRAM-based LUT | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm all-layer copper, up to 8 metal layers |
| Boîtier | 672-ball FineLine BGA (FBGA-672) | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch |
| Core Voltage | 1.5 V | — |
| Configuration Method | External SRAM configuration device (EPC series) | — |
| Temperature Grade | Industrial (-40 °C to +100 °C ambient) | — |
| Speed Grade | 6 | — |
| Embedded Memory | Embedded System Blocks (ESB), dual-port RAM / CAM | Enhanced System Blocks (ESBs) for dual-port RAM |
| DSP Blocks | MultiCore dedicated multipliers | — |
| Boundary Scan | JTAG (IEEE 1149.1) compliant | — |
| Clock Management | Dedicated PLL / clock tree circuitry | — |
| I/O Bank Count | [DATA_NEEDED: number of user I/O banks] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (per distributor listings) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Logic Elements / Cells | — | 24320 |
| System Gates | — | Approx. 900000 |
| Maximum User I/O | — | 492 |
| Operating Frequency | — | 236 MHz |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Seated Height (max) | — | 2.100 mm |
| Propagation Delay | — | 2.23 ns |
| Logic Family | — | CMOS |
| Température de fonctionnement | — | 0 °C to +85 °C (commercial, C9 grade) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport |
| LVDS Data Rate | — | Up to 1 Gbps (True-LVDS) |
| Configuration Interface | — | Serial / Parallel PROM, JTAG, passive parallel (enhanced) |
| Design Software | — | Quartus II (v5.1 or later) |