EP2A25F672I6 vs EP2A25F672C9N 对比
详细并排对比 EP2A25F672I6 出自 Intel 和 EP2A25F672C9N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A25F672I6 | EP2A25F672C9N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $178.00 | $195.00 |
| Family | APEX II | APEX II |
| Logic Elements (typical gates) | 25,000 | — |
| Fabric Architecture | SRAM-based LUT | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm all-layer copper, up to 8 metal layers |
| 封装 | 672-ball FineLine BGA (FBGA-672) | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch |
| Core Voltage | 1.5 V | — |
| Configuration Method | External SRAM configuration device (EPC series) | — |
| Temperature Grade | Industrial (-40 °C to +100 °C ambient) | — |
| Speed Grade | 6 | — |
| Embedded Memory | Embedded System Blocks (ESB), dual-port RAM / CAM | Enhanced System Blocks (ESBs) for dual-port RAM |
| DSP Blocks | MultiCore dedicated multipliers | — |
| Boundary Scan | JTAG (IEEE 1149.1) compliant | — |
| Clock Management | Dedicated PLL / clock tree circuitry | — |
| I/O Bank Count | [DATA_NEEDED: number of user I/O banks] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | Compliant (per distributor listings) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等级 | [DATA_NEEDED: moisture sensitivity level] | — |
| 安装类型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Logic Elements / Cells | — | 24320 |
| System Gates | — | Approx. 900000 |
| Maximum User I/O | — | 492 |
| Operating Frequency | — | 236 MHz |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Seated Height (max) | — | 2.100 mm |
| Propagation Delay | — | 2.23 ns |
| Logic Family | — | CMOS |
| 工作温度 | — | 0 °C to +85 °C (commercial, C9 grade) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport |
| LVDS Data Rate | — | Up to 1 Gbps (True-LVDS) |
| Configuration Interface | — | Serial / Parallel PROM, JTAG, passive parallel (enhanced) |
| Design Software | — | Quartus II (v5.1 or later) |