EP2A40B724C7N vs EP2A40B724C8ES Comparaison
Comparaison détaillée côte à côte de EP2A40B724C7N par Intel et EP2A40B724C8ES par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40B724C7N | EP2A40B724C8ES |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $175,00 | $162,00 |
| Family | APEX II | Field Programmable Gate Array (FPGA) |
| Series | EP2A40 | APEX II (EP2A) |
| Device Type | FPGA (Loadable PLD) | — |
| System Gates | 1.5 M | — |
| Logic Cells / Elements | 38,400 | — |
| Maximum Internal Performance | 562 MHz | — |
| Propagation Delay | 1.55 ns | — |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.575 V) | — |
| User I/O Lines | 536 | — |
| Boîtier | 724-pin FCBGA (PBGA) | 724-BBGA / FCBGA |
| JESD-30 Package Code | S-PBGA-B724 | — |
| Terminal Count | 724 | — |
| Output Function | MACROCELL | — |
| Plage de température de fonctionnement | 0 C to 85 C (commercial) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Logic Elements / Cells | — | 38,400 |
| Number of Gates (typical) | — | 655,360 |
| Number of I/O | — | 540 |
| Speed Grade | — | -8 (C8) |
| Température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Niveau MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |
| Tension d'alimentation | — | [DATA_NEEDED: VCCINT / VCCIO core and I/O voltages] |
| Process Node | — | [DATA_NEEDED: CMOS process technology] |
| Embedded Memory | — | Embedded System Blocks (ESB) |
| Programmable Logic Type | — | SRAM-based, in-system reconfigurable |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |
| Architecture | — | MultiCore interconnect with LABs and ESBs |