EP2A40B724I-7 vs EP2A40B724C7 Comparaison
Comparaison détaillée côte à côte de EP2A40B724I-7 par Altera et EP2A40B724C7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40B724I-7 | EP2A40B724C7 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $158,00 | $650,00 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 LE | — |
| Embedded Memory | 1.5 Mbit (ESB) | — |
| Maximum User I/O | [DATA_NEEDED: max user I/O count] | 540 |
| Number of PLLs | 4 | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| Speed Grade | -7 | — |
| Boîtier | BGA-724 (724-ball FineLine BGA) | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm |
| Package Footprint | 33 x 33 mm | — |
| Ball Pitch | 1.27 mm | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Peak Reflow Temperature | 220 C | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (lead-bearing FCBGA) |
| Configuration Mode | Enhanced configuration device / fast serial | — |
| Process Technology | [DATA_NEEDED: process node] | 0.15 µm CMOS, up to 8 metal layers, all-layer copper |
| I/O Standard Support | LVTTL / LVCMOS 1.5V, 1.8V, 2.5V, 3.3V | — |
| Logic Elements / Cells | — | 38,400 |
| Total System Gates | — | 1,500,000 |
| Embedded RAM Bits | — | 655,360 |
| Core Supply Voltage | — | 1.425 V to 1.575 V (typ. 1.5 V) |
| Maximum Internal Frequency | — | 562 MHz |
| PLLs | — | 4 |
| Température de fonctionnement | — | 0 °C to +85 °C (commercial) |
| I/O Standards Supported | — | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices |
| MultiVolt I/O Support | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| DDR Memory Support | — | Yes (via ESB / I/O circuitry) |