EP2A40B724I-8 vs EP2A40B724C8 Comparaison
Comparaison détaillée côte à côte de EP2A40B724I-8 par Altera et EP2A40B724C8 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40B724I-8 | EP2A40B724C8 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $280,00 | $615,00 |
| Family | APEX II | APEX II |
| Logic Elements (LEs) | 38,400 | — |
| Logic Array Blocks (LABs) | 3,840 | — |
| Embedded System RAM | 655,360 bits (655 Kbits) | — |
| Maximum User I/O | 540 | — |
| Boîtier | 724-ball FineLine BGA | — |
| Package Code | HBGA / S-PBGA-B724 | — |
| Speed Grade | -8 | — |
| Température de fonctionnement | -40C to +100C (Industrial) | 0 °C to 85 °C (TJ) |
| Core Supply Voltage | 1.5 V (1.425 V to 1.575 V) | 1.5 V (1.425 V to 1.575 V) |
| I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| PLLs | 4 | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status per datasheet] |
| Configuration Mode | JTAG / passive serial / passive parallel | — |
| Process Node | [DATA_NEEDED: process technology] | — |
| Device Logic Elements / Cells | — | 38400 |
| Total System Gates | — | ~1.5 M |
| Total RAM Bits | — | 655360 |
| Number of I/O | — | 540 |
| Number of Logic Gates | — | [DATA_NEEDED: exact gate count in cells vs system gates] |
| Maximum Internal Frequency | — | 376 MHz |
| Process Technology | — | 0.15 µm CMOS, all-layer copper, up to 8 metal layers |
| I/O Standards Supported | — | True-LVDS, LVPECL, PCML, HyperTransport (up to 1 Gbps) |
| Boîtier / Format | — | 724-BBGA, FCBGA (35 x 35 mm) |
| Supplier Device Package | — | 724-BGA |
| Shipping Media | — | Tray |
| Niveau de sensibilité à l'humidité (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |