EP2A40F1020C7ES vs EP2A40F1020C8 Comparaison
Comparaison détaillée côte à côte de EP2A40F1020C7ES par Intel et EP2A40F1020C8 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40F1020C7ES | EP2A40F1020C8 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $185,00 | $310,00 |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | — |
| Typical Gates | 1,500,000 | — |
| Embedded Memory | 655,360 bits | — |
| Maximum User I/O | 735 | — |
| Maximum Frequency | 562 MHz | — |
| Process Technology | 0.15 µm CMOS, all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | — |
| Boîtier | 1020-pin FC-FBGA | — |
| Speed Grade | C7 (with ES enhanced speed suffix) | — |
| High-Speed Interface | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport | — |
| Température de fonctionnement | [DATA_NEEDED: commercial/industrial grade] | 0 C to +85 C (commercial, 'C' suffix) |
| I/O Standards | LVTTL, LVCMOS, LVDS, LVPECL, PCML, HyperTransport, 1.5/1.8/2.5/3.3 V | — |
| PLLs | Up to 8 (per datasheet family feature) | — |
| Statut RoHS | [DATA_NEEDED] | [DATA_NEEDED: confirm per lot] |
| Programming Interface | JTAG (IEEE 1149.1), passive serial | — |
| Type de montage | Surface Mount (FC-FBGA) | — |
| Logic Family | — | CMOS |
| System Gates | — | 1,500,000 |
| Logic Cells | — | 38,400 |
| Macros / Macro Cells | — | 2,560 |
| Embedded RAM | — | [DATA_NEEDED: total ESB bits] |
| Maximum Internal Frequency | — | 376 MHz |
| Propagation Delay | — | 1.55 ns |
| User I/O Pins | — | 735 |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage (VCCIO) | — | MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| Package Type | — | FC-FBGA (FineLine BGA) |
| Package Pin Count | — | 1020 |
| Package Dimensions | — | 33 x 33 mm |
| Ball Pitch | — | 1.0 mm |
| Configuration Interface | — | JTAG / Altera serial |
| Design Toolchain | — | Quartus II (legacy version 4.x or earlier recommended) |