EP2A40F1020C9ES vs EP2A40F1020C7ES Comparaison
Comparaison détaillée côte à côte de EP2A40F1020C9ES par Altera et EP2A40F1020C7ES par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP2A40F1020C9ES - APEX II FPGA 1.5M Gates 38400 Cells 366MHz | Altera
EP2A40F1020C9ES ObsoleteComparaison des spécifications
| Paramètre | EP2A40F1020C9ES | EP2A40F1020C7ES |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $98,00 | $185,00 |
| Family | APEX II | APEX II |
| System Gates | 1.5 M | — |
| Logic Cells / Elements | 38,400 | — |
| Maximum Internal Clock Frequency | 366 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS, all-layer copper, up to 8 metal layers |
| Core Supply Voltage | 1.5 V | — |
| Boîtier | 1020-pin FC-FBGA | 1020-pin FC-FBGA |
| Package Type | Flip-Chip Fine-Pitch Ball Grid Array | — |
| Type de montage | Surface Mount | Surface Mount (FC-FBGA) |
| Embedded Memory | Embedded System Blocks (ESBs) - RAM/ROM | 655,360 bits |
| I/O Standards | LVDS and other high-speed standards (per family datasheet) | LVTTL, LVCMOS, LVDS, LVPECL, PCML, HyperTransport, 1.5/1.8/2.5/3.3 V |
| RAM Support | Synchronous and asynchronous | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial/industrial grade] |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 38,400 |
| Typical Gates | — | 1,500,000 |
| Maximum User I/O | — | 735 |
| Maximum Frequency | — | 562 MHz |
| Core Voltage | — | 1.5 V |
| Speed Grade | — | C7 (with ES enhanced speed suffix) |
| High-Speed Interface | — | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport |
| PLLs | — | Up to 8 (per datasheet family feature) |
| Programming Interface | — | JTAG (IEEE 1149.1), passive serial |