EP2A40F672C6 vs EP2A40B724C7 Comparaison
Comparaison détaillée côte à côte de EP2A40F672C6 par Altera et EP2A40B724C7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40F672C6 | EP2A40B724C7 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $105,00 | $650,00 |
| Family | APEX II | APEX II |
| Device | EP2A40 | — |
| Logic Elements (typical) | 40,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O count] | — |
| Boîtier | 672-ball FineLine BGA (FBGA-672) | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm |
| Speed Grade | C6 (commercial) | — |
| Température de fonctionnement | Commercial (0C to +85C) | 0 °C to +85 °C (commercial) |
| Process Technology | 0.18-micron CMOS | 0.15 µm CMOS, up to 8 metal layers, all-layer copper |
| Configuration Memory | SRAM-based | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| PLL Support | Yes | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (lead-bearing FCBGA) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Lifecycle | Obsolete / EOL (per Intel/Altera product discontinuation notice) | — |
| Logic Elements / Cells | — | 38,400 |
| Total System Gates | — | 1,500,000 |
| Embedded RAM Bits | — | 655,360 |
| Maximum User I/O | — | 540 |
| Core Supply Voltage | — | 1.425 V to 1.575 V (typ. 1.5 V) |
| Maximum Internal Frequency | — | 562 MHz |
| PLLs | — | 4 |
| I/O Standards Supported | — | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices |
| MultiVolt I/O Support | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| DDR Memory Support | — | Yes (via ESB / I/O circuitry) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |