EP2A40F672C9 vs EP2A40F672C6N Comparaison
Comparaison détaillée côte à côte de EP2A40F672C9 par Altera et EP2A40F672C6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera
EP2A40F672C9 ⚠ Dernier achat
Comparaison des spécifications
| Paramètre | EP2A40F672C9 | EP2A40F672C6N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $62,00 | $165,00 |
| Family | APEX II | APEX II |
| Device Family | APEX II PLD | — |
| Logic Elements / Cells | 38,400 | — |
| System Gates | 1.5 M | — |
| Macros | 2,560 | — |
| User I/Os | 492 | — |
| Nombre de broches | 672 | — |
| Boîtier | 672-BBGA, FC-FBGA (FineLine) | 672-ball FineLine BGA |
| Package Size | 27 mm × 27 mm, 1 mm ball pitch | — |
| Core Voltage | 1.5 V | 1.5 V |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | SRAM-based, 0.18 um (per family datasheet) |
| Logic Family | CMOS | — |
| Propagation Delay | 1.55 ns | — |
| Internal Speed Grade | 366 MHz | — |
| Température de fonctionnement | 0 °C to 85 °C (commercial) | Commercial (0C to +85C) |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements | — | 40,000 |
| Maximum System Gates | — | 1,125,000 |
| Embedded RAM Bits | — | 442,368 |
| Embedded System Blocks (ESBs) | — | 160 |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Speed Grade | — | C6 (per part number suffix) |
| Configuration Methods | — | Passive Serial, Passive Parallel, JTAG |
| PLL Count | — | [DATA_NEEDED: PLL count] |