EP2A40F672I9N vs EP2A25F672I9N Comparaison
Comparaison détaillée côte à côte de EP2A40F672I9N par Altera et EP2A25F672I9N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40F672I9N | EP2A25F672I9N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 395,00 | $215,00 |
| Family | APEX II | APEX II |
| Technology | 0.15 um CMOS | — |
| Logic Elements | 38400 cells | — |
| System Gates | 1.5 M | 900,000 (typical) |
| Maximum Operating Frequency | 366 MHz | — |
| Core Supply Voltage | 1.5 V | — |
| User I/O Count | 492 | — |
| Embedded Memory | [DATA_NEEDED: total ESB bits] | — |
| Boîtier | 672-ball FC-FBGA | 672-pin FC-FBGA |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL | — |
| True-LVDS Data Rate | 840 Mbps per channel | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG, EPC device | — |
| Temperature Grade | Industrial -40C to +100C (I9 suffix) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS compliance of I9N suffix] | [DATA_NEEDED: confirmed] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | APEX II (EP2A25) |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Elements / Cells | — | 24,320 |
| Process Technology | — | 0.15 µm CMOS |
| Maximum Internal Frequency | — | 236 MHz |
| Propagation Delay (tpd) | — | 2.23 ns |
| Core Supply Voltage (VCCINT) | — | 1.5 V nominal (1.425 V to 1.525 V) |
| I/O Supply Voltage | — | [DATA_NEEDED: VCCIO range] |
| Température de fonctionnement | — | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Speed Grade | — | 9 (fastest commercial APEX II) |
| Embedded System Blocks (ESB) | — | Yes (on-chip RAM/ROM) |
| PLLs | — | 4 |
| Configuration | — | JTAG / in-system programmable |
| Niveau MSL | — | [DATA_NEEDED] |
| AEC-Q100 | — | not_applicable |