EP2A40F724 vs EP2A40F780 Comparaison
Comparaison détaillée côte à côte de EP2A40F724 par Altera et EP2A40F780 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40F724 | EP2A40F780 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $168,00 | $142,00 |
| Family | APEX II | APEX II |
| Series | EP2A | — |
| Logic Elements | 38400 | 30,000 |
| System Gates | 1,500,000 (typical) | — |
| Maximum User I/O | 498 | — |
| Embedded RAM Bits | 655360 | — |
| CAM Blocks | Yes | — |
| PLLs | 4 | — |
| Global Clock Networks | 16 | — |
| Core Voltage | 1.5 V | [DATA_NEEDED: VCCINT] |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Boîtier | 724-ball FineLine BGA (F724) | 780-ball FineLine BGA (FBGA) |
| Température de fonctionnement | 0C to +85C (commercial) | [DATA_NEEDED: temperature grade] |
| Process Technology | 0.15 µm CMOS | [DATA_NEEDED: process node] |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JTAG (IEEE 1149.1) / Altera ByteBlaster | — |
| Device | — | EP2A40 |
| Typical Gates | — | 1,500,000 |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Type de montage | — | Surface Mount |
| Configuration Memory | — | SRAM-based |
| Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming File Format | — | .sof/.pof via Quartus II |
| I/O Voltage | — | [DATA_NEEDED: VCCIO range] |