EP2A40F724 vs EP2A40F780 比較
詳細な並列比較: EP2A40F724 メーカー: Altera および EP2A40F780 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2A40F724 | EP2A40F780 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $168.00 | $142.00 |
| Family | APEX II | APEX II |
| Series | EP2A | — |
| Logic Elements | 38400 | 30,000 |
| System Gates | 1,500,000 (typical) | — |
| Maximum User I/O | 498 | — |
| Embedded RAM Bits | 655360 | — |
| CAM Blocks | Yes | — |
| PLLs | 4 | — |
| Global Clock Networks | 16 | — |
| Core Voltage | 1.5 V | [DATA_NEEDED: VCCINT] |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| パッケージ | 724-ball FineLine BGA (F724) | 780-ball FineLine BGA (FBGA) |
| 動作温度 | 0C to +85C (commercial) | [DATA_NEEDED: temperature grade] |
| Process Technology | 0.15 µm CMOS | [DATA_NEEDED: process node] |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JTAG (IEEE 1149.1) / Altera ByteBlaster | — |
| Device | — | EP2A40 |
| Typical Gates | — | 1,500,000 |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| 実装タイプ | — | Surface Mount |
| Configuration Memory | — | SRAM-based |
| Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming File Format | — | .sof/.pof via Quartus II |
| I/O Voltage | — | [DATA_NEEDED: VCCIO range] |