EP2A70B724I7N vs EP2A70B724C7N Comparaison
Comparaison détaillée côte à côte de EP2A70B724I7N par Intel et EP2A70B724C7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A70B724I7N | EP2A70B724C7N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $218,00 | $188,00 |
| Family | APEX II | APEX II (EP2A70) |
| Logic Elements | 67,200 cells | — |
| System Gates | 3,000,000 | 3,000,000 |
| Maximum Operating Frequency | 420 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| Boîtier | 724-pin FCBGA | 724-pin FCBGA (Flip-Chip BGA) |
| User I/O Pins | 536 | 536 |
| Propagation Delay | 2.17 ns | — |
| Operating Temperature Grade | Industrial (-40C to +100C, suffix I) | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| Embedded Memory | [DATA_NEEDED: ESB memory size] | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM |
| I/O Standards Supported | LVDS, PCI-X, HSTL, SSTL, LVTTL, LVCMOS | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Technology | — | 0.15 µm CMOS |
| Logic Cells / Logic Elements | — | 67,200 |
| Maximum Internal Frequency | — | 420 MHz |
| Propagation Delay (typ.) | — | 2.17 ns |
| Macrocells (memory blocks reference) | — | 16 |
| Core Supply Voltage | — | 1.5 V nominal |
| I/O Supply Voltage | — | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) |
| Température de fonctionnement | — | 0 °C to +85 °C (Commercial) |
| Ball Pitch | — | 1.27 mm |
| Seated Height | — | 3.5 mm |
| Configuration Method | — | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) |
| PLL Count | — | [DATA_NEEDED: PLL count] |