EP2AGX65CU17I5G vs EP2AGX65CU17C5N Comparaison
Comparaison détaillée côte à côte de EP2AGX65CU17I5G par Intel et EP2AGX65CU17C5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2AGX65CU17I5G | EP2AGX65CU17C5N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Unknown | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $178,40 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | Arria II GX | — |
| Logic Elements | 60,214 | 60,214 |
| Programmable Logic Bits | 5,371,904 | — |
| User I/O Count | 156 | — |
| Boîtier | 358-ball LFBGA, FCBGA | 358-ball FC-UFBGA (UBGA) |
| Number of Terminals | 358 | — |
| Terminal Form | Ball | — |
| Package Code | LFBGA | — |
| Package Shape | Square | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Logic Cell Count | 60,214 | — |
| I/O Count | 156 | — |
| Statut RoHS | Compliant | — |
| Lead Free Status | Not stated in verified data | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Core Voltage | [DATA_NEEDED: core voltage] | 0.9 V |
| I/O Voltage Support | [DATA_NEEDED: I/O voltage support] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Maximum Transceiver Data Rate | [DATA_NEEDED: maximum transceiver data rate] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Arria II GX |
| LABs/CLBs | — | 2,530 |
| Total Memory Bits | — | 5,371,904 bits (4.4 Mb) |
| Maximum User I/O | — | 156 |
| User I/O Banks | — | 9 (typical, package-dependent) |
| Process Technology | — | 40 nm TSMC low-power |
| Transceivers | — | Up to 16 multi-gigabit transceivers |
| Max Transceiver Data Rate | — | 6.375 Gbps |
| PLLs | — | 8 |
| DSP Blocks | — | 6 × 6 hardened multipliers |
| Speed Grade | — | C5 (middle-speed) |
| Temperature Grade | — | N (extended, -40 °C to +100 °C Tj) |
| Hard PCIe Gen1/Gen2 | — | Yes (with PIPE interface) |
| Configuration Modes | — | FPP, PS, JTAG, EPCS |