EP2AGZ300FF35I3G vs EP2AGX190FF35I3G Comparaison
Comparaison détaillée côte à côte de EP2AGZ300FF35I3G par Intel et EP2AGX190FF35I3G par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP2AGX190FF35I3G - Arria II GX FPGA 190K LE | Intel | Altera
EP2AGX190FF35I3G ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP2AGZ300FF35I3G | EP2AGX190FF35I3G |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 230,00 | $1 840,00 |
| Family | Arria II GZ | Arria II GX |
| Logic Elements (LE) | 300000 | 181,165 |
| Number of User I/O | 554 (maximum) | — |
| Number of Transceivers | 8 | — |
| Transceiver Data Rate | Up to 6.375 Gbps | — |
| Process Node | 40 nm | 40 nm |
| Température de fonctionnement | -40C to +100 C (I3 industrial) | -40 °C to +100 °C (industrial, suffix I) |
| Boîtier | 1152-ball FBGA (FF35) | 1152-ball FC-FBGA (FF35), 35 mm body |
| Type de montage | Surface Mount | Surface Mount (flip-chip BGA) |
| Tension d'alimentation | [DATA_NEEDED: core and I/O supply voltage values] | — |
| Embedded Memory (Mbits) | 16.4 | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks] | — |
| PLLs | [DATA_NEEDED: number of PLLs] | [DATA_NEEDED: PLL count] |
| Memory Interfaces | DDR3, QDRII+, RLDRAM II | — |
| Configuration Method | Serial, Parallel, JTAG | — |
| Statut RoHS | Compliant | Compliant (suffix G) |
| Niveau MSL | 3 (168 hours) | — |
| Lead-Free | Yes | Yes |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count] |
| User I/O Pins | — | 612 |
| Embedded Memory (bits) | — | 10,177,536 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Transceivers | — | 8 high-speed transceiver channels (multi-gigabit) |
| Embedded Multipliers | — | [DATA_NEEDED: 18x18 multiplier count] |
| Core Voltage | — | 0.9 V |
| I/O Voltage Standards | — | 1.2 V to 3.3 V (LVTTL, LVCMOS, LVDS, HSTL, SSTL) |
| Speed Grade | — | 3 |
| Ball Pitch | — | [DATA_NEEDED: 1.0 mm (typical for FF35)] |
| Programming Toolchain | — | Quartus II / Quartus Prime |