EP2S15F672C3 vs EP2S15F672C4 Comparaison
Comparaison détaillée côte à côte de EP2S15F672C3 par Intel et EP2S15F672C4 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S15F672C3 | EP2S15F672C4 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $142,30 | $235,00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 15,600 | 15,600 |
| Embedded Memory (bits) | 419,328 | — |
| DSP Blocks (18-bit multipliers) | 156 | — |
| Maximum User I/O | 366 | — |
| Core Voltage | 1.2 V | — |
| Process Technology | 90 nm CMOS | — |
| Maximum Internal Frequency | [DATA_NEEDED: max internal clock MHz] | — |
| Boîtier | 672-ball FC-FBGA | 672-ball FineLine BGA (FBGA) |
| Type de montage | Surface Mount | — |
| Operating Temperature Grade | Commercial (C3 suffix) | — |
| Speed Grade | C3 (third commercial speed bin) | 4 |
| PLLs | [DATA_NEEDED: number of PLLs] | 6 |
| Global Clock Networks | [DATA_NEEDED: number of global clocks] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance per Altera product page] |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL moisture sensitivity level] |
| Embedded Memory Bits | — | 419,328 bits |
| DSP Blocks | — | 156 (approximate, per Stratix II family) |
| Maximum User I/Os | — | 366 |
| Process Node | — | 90 nm |
| Température de fonctionnement | — | Commercial (0C to +85C, 'C' suffix) |
| Configuration Method | — | Serial / Parallel (passive serial, fast passive parallel, JTAG) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish status] |