EP2S60F1020C5 vs EP2S60F1020C4N Comparaison
Comparaison détaillée côte à côte de EP2S60F1020C5 par Intel et EP2S60F1020C4N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S60F1020C5 | EP2S60F1020C4N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $995,00 | $67,00 |
| Family | Stratix II | Stratix II (EP2S60) |
| Logic Elements | 60,440 | 60,440 |
| Adaptive Logic Modules (ALMs) | 30,220 | 30,220 (approx.) |
| Equivalent Logic Elements | 60,440 | — |
| Total RAM Bits | 2,544,192 | — |
| DSP Blocks | 256 (18x18 multipliers) | — |
| Maximum User I/O | 718 | — |
| Embedded Transceivers | 12 (up to 6.375 Gbps) | — |
| PLLs | 4 | — |
| Global Clock Networks | 16 | — |
| Boîtier | 1020-ball FC-FBGA (33x33 mm, 1.0 mm pitch) | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Speed Grade | C5 (commercial) | — |
| Temperature Grade | Commercial (0C to +85C) | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | EU RoHS compliant with exemption (per Arrow listing) |
| Series | — | Stratix II |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory (bits) | — | 2,544,192 |
| Embedded Memory Blocks | — | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | — | Up to 48 (24 per DSP block column pair typical) |
| User I/Os | — | 718 |
| Maximum Core Frequency | — | 711.24 MHz (per Arrow listing) |
| Operating Temperature Grade | — | Commercial (C4 suffix indicates commercial, speed grade 4) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs / Clock Networks | — | Yes - on-chip PLLs and global clock networks |