EP2S60F1020C5 vs EP2S60F1020C4N 对比

详细并排对比 EP2S60F1020C5 出自 Intel 和 EP2S60F1020C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S60F1020C5 EP2S60F1020C4N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $995.00 $67.00
Family Stratix II Stratix II (EP2S60)
Logic Elements 60,440 60,440
Adaptive Logic Modules (ALMs) 30,220 30,220 (approx.)
Equivalent Logic Elements 60,440 —
Total RAM Bits 2,544,192 —
DSP Blocks 256 (18x18 multipliers) —
Maximum User I/O 718 —
Embedded Transceivers 12 (up to 6.375 Gbps) —
PLLs 4 —
Global Clock Networks 16 —
封装 1020-ball FC-FBGA (33x33 mm, 1.0 mm pitch) 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA)
Speed Grade C5 (commercial) —
Temperature Grade Commercial (0C to +85C) —
Process Technology 90 nm CMOS 90 nm CMOS
Core Voltage 1.2 V 1.2 V
安装类型 Surface Mount (BGA) Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL level] —
RoHS 状态 [DATA_NEEDED: RoHS status] EU RoHS compliant with exemption (per Arrow listing)
Series — Stratix II
Logic Array Blocks (LABs) — 3,022
Embedded Memory (bits) — 2,544,192
Embedded Memory Blocks — M512/M4K/M-RAM TriMatrix memory
DSP Blocks (18-bit x 18-bit) — Up to 48 (24 per DSP block column pair typical)
User I/Os — 718
Maximum Core Frequency — 711.24 MHz (per Arrow listing)
Operating Temperature Grade — Commercial (C4 suffix indicates commercial, speed grade 4)
Configuration Modes — Passive Serial, Fast Passive Parallel, JTAG
PLLs / Clock Networks — Yes - on-chip PLLs and global clock networks

数据手册与资源

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