EP2S60F67214N vs EP2S60F672C3N Comparaison
Comparaison détaillée côte à côte de EP2S60F67214N par Altera et EP2S60F672C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S60F67214N | EP2S60F672C3N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $232,00 | $1 175,00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 60,440 LE | — |
| Total RAM Bits | 2,544,192 bit (2.5 Mbit) | — |
| DSP Blocks | 12 | — |
| Phase-Locked Loops (PLLs) | 4 | — |
| Boîtier | 672-ball FBGA (FineLine BGA) | 672-pin FC-FBGA |
| Type de montage | Surface Mount | Surface Mount |
| Speed Grade | I4 (industrial, fast) | C3 (slower speed grade) |
| Température de fonctionnement | -40C to +100C (industrial) | 0C to +85C (commercial grade) |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V (typical) | — |
| I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for FBGA-672] | — |
| Configuration | SRAM-based, configured via bitstream | — |
| Statut RoHS | Lead-free / RoHS compliant | unknown |
| Niveau MSL | 3 (168 hours floor life) | — |
| Logic Elements (LE) | — | 60,440 |
| Logic Array Blocks (LABs) | — | 3,022 |
| Adaptive Logic Modules (ALMs) | — | 24,176 |
| Total Embedded Memory | — | 2,544,192 bits (2.5 Mbits) |
| User I/O Pins | — | 492 |
| User I/O Banks | — | 8 |
| Core Supply Voltage (VCCINT) | — | 1.2 V |
| I/O Supply Voltage (VCCIO) | — | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Pre-Driver Supply (VCCPD) | — | 3.3 V |
| Maximum Internal Clock Frequency | — | 816.99 MHz |
| PLLs | — | 4 |
| Global Clock Networks | — | 16 |
| Lead-Free | — | unknown |