EP2S60F672C5 vs EP2S60F672C3 Comparaison
Comparaison détaillée côte à côte de EP2S60F672C5 par Intel et EP2S60F672C3 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S60F672C5 | EP2S60F672C3 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $410,85 | $1 033,14 |
| Family | Stratix II | Stratix II |
| Device Family | Stratix II FPGA | — |
| Logic Elements | 60,440 | 60,440 |
| Configurable Logic Blocks (CLBs) | 24,176 | — |
| Total RAM Bits | 2,544,192 bits | 2,544,192 |
| Maximum User I/Os | 492 | — |
| Operating Frequency | Up to 609.76 MHz | — |
| Core Voltage | 1.2 V | 1.2 V |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Boîtier | 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch) | 672-BBGA, FC-FBGA, 35 x 35 mm, 1.0 mm pitch |
| Type de montage | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C5 suffix) | — |
| Plage de température de fonctionnement | 0°C to +85°C | — |
| Number of PLLs | 4 | — |
| DSP Blocks | 12 (dedicated 18 × 18 multipliers) | [DATA_NEEDED: DSP block count] |
| I/O Standards | LVDS, LVTTL, SSTL, HSTL, PCI-X | — |
| Configuration Scheme | Fast Passive Parallel, JTAG, Active Serial | — |
| Statut RoHS | Non-RoHS (legacy product, pre-RoHS production runs) | [DATA_NEEDED: RoHS status] |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Embedded Multiplier Blocks | — | [DATA_NEEDED: 9x9 multiplier count] |
| User I/Os | — | 492 |
| PLLs | — | 4 |
| Global Clocks | — | [DATA_NEEDED: global clock count] |
| Speed Grade | — | C3 |
| Configuration Modes | — | PS, PPS, PPA, FPP, JTAG |
| Température de fonctionnement | — | 0C to +85C (commercial) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |