EP3SE50F780C4N vs EP3SE50F780C4LG Comparaison
Comparaison détaillée côte à côte de EP3SE50F780C4N par Intel et EP3SE50F780C4LG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP3SE50F780C4LG - 47.5K LE Stratix III E FPGA, 488 I/O, FBGA-780 | Intel
EP3SE50F780C4LG ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP3SE50F780C4N | EP3SE50F780C4LG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 430,00 | $289,50 |
| Family | Stratix III E | Stratix III E (Enhanced) |
| Logic Elements (LE) | 47,500 | — |
| Embedded Memory Bits | 5,760,000 | — |
| Embedded Memory (M9K/M144K blocks) | 488 (per family datasheet) | — |
| Number of LABs | 1900 | — |
| Maximum User I/Os | 488 | — |
| DSP Blocks (18x18 multipliers) | 432 | [DATA_NEEDED: DSP block count] |
| PLLs | 12 (per family datasheet) | — |
| Maximum Operating Frequency | 717 MHz | — |
| Transceiver Channels | Up to 12 (per family, model-dependent) | — |
| Transceiver Data Rate | Up to 6.375 Gbps (per Stratix III E family) | — |
| Process Node | 40 nm | — |
| Boîtier | 780-Ball FBGA, 29 mm x 29 mm, 1.0 mm pitch | 780-BBGA, FCBGA (FBGA-780, 1.0 mm pitch) |
| Type de montage | Surface Mount (BGA) | Surface Mount (SMT) |
| Tension d'alimentation | Core 0.9 V, I/O 1.2 V-3.3 V (multi-rail) | — |
| Température de fonctionnement | 0C to +85C (C4 commercial grade) | — |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel | — |
| Statut RoHS | Lead-free / RoHS compliant | — |
| Niveau MSL | 3 (per JEDEC J-STD-020, FBGA package) | — |
| Hard Memory Controller | DDR2/DDR3 SDRAM (per Stratix III E family) | — |
| Logic Elements | — | 47,500 LE |
| Adaptive Logic Modules (ALMs) | — | 19,000 ALM |
| Embedded Memory | — | 5.49 Mbit |
| User I/Os | — | 488 I/O |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Transceivers | — | [DATA_NEEDED: transceiver count and rate] |
| Process Technology | — | 40 nm TSMC low-power CMOS |
| Speed Grade | — | -4 (fastest commercial) |
| Operating Temperature (Commercial) | — | 0 C to +85 C |
| Core Voltage (VCCINT) | — | 0.9 V / 1.0 V / 1.1 V (programmable) |
| Tension d'alimentation de fonctionnement | — | 1.1 V (logic core nominal) |
| Lead-Free Status | — | Pb-free (LG suffix) |
| Niveau de sensibilité à l'humidité (MSL) | — | MSL 3 (per JEDEC J-STD-020) |
| RoHS Compliance | — | Compliant |