EP3SE80F1152C3N vs EP3SE110F1152C3N Comparaison
Comparaison détaillée côte à côte de EP3SE80F1152C3N par Intel et EP3SE110F1152C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP3SE110F1152C3N - Stratix III E FPGA, 107.5K LE, FC-FBGA-1152 | Intel
EP3SE110F1152C3N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP3SE80F1152C3N | EP3SE110F1152C3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 690,00 | $1 560,00 |
| Series | Stratix III E | Stratix III |
| Logic Elements (LEs) | 80,000 | — |
| Total Memory Bits | 6,843,392 bits | — |
| Number of LABs/CLBs | 3200 | — |
| Number of User I/O | 744 | — |
| Nombre de sorties | 744 | — |
| Boîtier / Format | 1152-BBGA, FCBGA (FineLine BGA) | — |
| Température de fonctionnement | 0C to +85C (commercial, C3 grade) | 0 °C to 85 °C (commercial) |
| Speed/Power Grade | C3 | — |
| Process Technology | 40 nm CMOS | 65 nm TSMC |
| Type de montage | Surface Mount | Surface Mount |
| Lead Free | Yes | — |
| Niveau MSL | 3 (per JEDEC J-STD-020) | — |
| Configuration Memory | SRAM-based, volatile (needs external config device) | — |
| Statut RoHS | Compliant | — |
| Family | — | Stratix III E |
| Logic Elements (LE) | — | 107,500 |
| Logic Array Blocks (LABs) | — | 4,300 |
| Total RAM Bits | — | 8,936,448 |
| User I/Os | — | 744 |
| Operating Frequency (max) | — | 500 MHz |
| Core Supply Voltage | — | 1.1 V nominal |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply range] |
| Package Type | — | FC-FBGA-1152 (flip-chip BGA) |
| Speed Grade | — | C3 |
| Style de montage | — | SMD/SMT (Tray) |
| DSP Blocks | — | Yes (embedded multipliers) |
| Type de mémoire | — | M9K and M144K block RAM |
| External Memory Support | — | DDR/DDR2/DDR3 with read/write leveling |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | Yes (per Altera/Intel datasheet family convention) |