EP3SL200H780C4 vs EP3SL200H780C3N Comparaison
Comparaison détaillée côte à côte de EP3SL200H780C4 par Altera et EP3SL200H780C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP3SL200H780C4 | EP3SL200H780C3N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 210,00 | $4 995,00 |
| Series | Stratix III L | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 200,000 | 200,000 |
| Number of LABs/CLBs | 8000 | — |
| Total RAM Bits | 10,901,504 | — |
| Number of I/O | 488 | — |
| Number of Gates | [DATA_NEEDED: total gate count not in source data] | — |
| Voltage - Supply | 0.9 V (core), 1.1 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V (I/O) | — |
| Température de fonctionnement | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Internal Operating Frequency | Up to 800 MHz | — |
| Type de montage | Surface Mount | Surface Mount |
| Boîtier / Format | 780-BBGA, FCBGA | — |
| Supplier Device Package | 780-FCBGA | — |
| Process Node | 40 nm TSMC | 40 nm |
| Multiplier Count (9-bit) | 488 | — |
| Statut RoHS | Compliant (lead-free) | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | 3 |
| Family | — | Stratix III L (low-power) |
| Embedded Memory Bits | — | 10,901,504 bits |
| Logic Array Blocks (LABs) | — | 8,000 |
| User I/Os | — | 488 |
| Boîtier | — | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| Maximum Internal Clock Frequency | — | 800 MHz |
| Transceivers | — | 24 channels, up to 3.75 Gbps |
| DSP Blocks | — | 384 |
| Speed Grade | — | C3 (commercial, -3 speed) |
| Voltage - Core | — | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | — | 1.2 V to 3.3 V (VCCIO banks) |
| Lead-Free / RoHS | — | Yes |
| Mounting Pitch | — | 1.0 mm ball pitch |
| PLLs | — | 12 (Stratix III PLL array) |
| Configuration | — | JTAG IEEE Std 1149.1, passive/active serial |