EP3SL340H1152I4 vs EP3SL340H1152I4L Comparaison
Comparaison détaillée côte à côte de EP3SL340H1152I4 par Intel et EP3SL340H1152I4L par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP3SL340H1152I4 | EP3SL340H1152I4L |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15 100,00 | $4 100,00 |
| Series | Stratix III L | — |
| Logic Elements (LE) | 337,500 | — |
| Embedded Memory | 18,821,440 bits | M9K + M144K blocks |
| User I/O Pins | 744 | 744 |
| Logic Array Blocks (LABs) | 13,500 | 13,500 |
| Operating Frequency | 717 MHz (max fabric speed) | — |
| Process Technology | 65 nm CMOS | — |
| Core Voltage | 1.1 V | 0.9 V |
| Boîtier | 1152-ball FCBGA / HBGA | 1152-ball FC-HFBGA (FCBGA) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (I4: -40C to +100C junction) | — |
| I/O Standards Supported | LVDS, LVPECL, HSTL, SSTL, LVCMOS, LVTTL | — |
| Memory Interface Hard IP | DDR / DDR2 / DDR3 SDRAM controllers with PHY | — |
| Statut RoHS | Compliant | Compliant (per Intel/Altera product page) |
| Lead-Free | Yes | Yes (Pb-free BGA balls) |
| Family | — | Stratix III L |
| Logic Elements | — | 337,500 |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Total Memory Bits | — | 18,221,440 bits |
| DSP Blocks (18x18 Multipliers) | — | [DATA_NEEDED: multiplier count] |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Process Node | — | 65 nm |
| Température de fonctionnement | — | -40C to +100C (industrial) |
| Speed Grade | — | 4 |
| PLLs | — | [DATA_NEEDED: PLL count] |
| High-Speed Transceivers | — | [DATA_NEEDED: transceiver count] |
| JTAG Support | — | IEEE Std 1149.1 boundary-scan |
| Configuration | — | FPGA, SRAM-based, in-system programmable |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |