EP610DC-20 vs EP610DC-30 Comparaison
Comparaison détaillée côte à côte de EP610DC-20 par Intel et EP610DC-30 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610DC-20 | EP610DC-30 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,85 | $10,40 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Classic EP610 | EP610 (Classic Device Family) |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 16 |
| I/O Pins | 16 (bidirectional) | 16 (with output enable) |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 30 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Température de fonctionnement | 0 °C to 70 °C (commercial) | Commercial (0C to +70C) |
| Boîtier | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CERDIP (windowed) |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| Type de montage | Through-hole | Through-Hole |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |