EP610DC-20 - 24-Pin CMOS UV PLD, 22ns Delay | Altera/Intel
Référence : EP610DC-20 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $24.5 | $24,50 |
| 10 | $21.95 | $219,50 |
| 100 | $19.2 | $1 920,00 |
| 500 | $17.4 | $8 700,00 |
| 1 000 | $15.85 | $15 850,00 |
EP610DC-20 Présentation
A Programmable Logic Device (PLD) is a digital integrated circuit whose internal logic and interconnect can be configured by the end user after manufacture, bridging the gap between discrete 74-series logic gates and fixed-function ASICs. The EP610 family is a 'Classic' generation EPLD fabricated on Altera's UV-erasable CMOS process, meaning the configuration is stored in floating-gate memory cells that can be cleared with approximately 20 minutes of UV-C exposure through the package window (the ceramic CDIP body provides this window). In the modern taxonomy, PLDs sit under the broader umbrella of programmable logic devices -> EPLD -> Classic UV-PLD -> semiconductor. They are positioned above simple PALs (smaller arrays, no registered outputs) and below modern CPLDs and FPGAs (larger logic capacity, in-system programmability, SRAM or flash-based configuration).
Key features of the EP610DC-20 include 16 macrocells with selectable D/T/JK flip-flops, a single 5 V supply, a pin-compatible speed-grade family with 20/15/10 ns tPD options (EP610DC-20/DC-15/DC-10), 160 product terms (also called 'p-terms'), and a dedicated clock/clear architecture. Each macrocell drives one of the 16 bidirectional I/O pins, and 4 pins are dedicated inputs only, giving a usable logic capacity of approximately 24 pins total. The device is supported by the legacy Altera MAX+PLUS II development environment (and MAX II), which compiles AHDL, VHDL, or schematic designs into the JEDEC fuse-map for programming.
The architecture is a classic AND-OR-NOT PLA feeding a configurable output macrocell. Each macrocell has a programmable output polarity, a tri-state buffer, and an optional flip-flop (D, T, JK, or latch). Product-term allocation is fixed (no expander chain), which simplifies timing analysis: all signals reach the OR array with a single tPD delay. This deterministic timing is one of the main reasons EPLDs were used in place of discrete TTL or early FPGAs in the 1980s and 1990s for glue logic, address decoding, and state machines.
Typical applications include legacy bus-interface glue logic (e.g., address decoding for ISA, VME, or STD-bus cards), state-machine controllers for industrial equipment, register and counter arrays replacing multiple 74LS/74F packages, and pin-compatible retrofits for systems that were originally designed around the EP610 family. The 24-pin CDIP-24 ceramic package makes it especially suitable for military, aerospace, and high-reliability programs where a UV-clearable hermetic device is preferred over plastic UV-windowless plastic PLDs.
When designing with this part, note that the configuration is volatile until programmed and that the ceramic DIP provides a quartz window for UV erasure. Programming requires an Altera-compatible parallel programmer (e.g., LogiCade, BP Microsystems) since modern USB programmers do not target this legacy family. Decoupling requires 0.1 µF ceramic capacitors on every VCC pin, plus a bulk tantalum or electrolytic cap on the board-level 5 V rail.
This page synthesizes distributor pricing, drop-in alternative MPNs (including same-family EP610DC-15 and EP610DC-10), legacy-programming guidance, and practical design notes not found in a single manufacturer datasheet.
Alternatives de remplacement direct pour EP610DC-20 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP610DC-20 (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Family, Propagation Delay (tPD), Technology.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP610DC-15
✅ Remplacement direct✓ En stock
$7.95 / unité
Voir la fiche technique →EP610DC-10
✅ Remplacement direct✓ En stock
$7.95 / unité
Voir la fiche technique →EP610DC-25
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EP610PC-20
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$47.8 / unité
Voir la fiche technique →EP610DC-30
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$10.4 / unité
Voir la fiche technique →EP610LC-20
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EP610DC-20 Valeurs maximales et caractéristiques électriques
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | Classic EP610 |
| Logic Macrocells | 16 |
| Dedicated Inputs | 4 |
| I/O Pins | 16 (bidirectional) |
| Total Usable Pins | 20 |
| Product Terms (p-terms) | 160 |
| Propagation Delay (tPD) | 22 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Température de fonctionnement | 0 °C to 70 °C (commercial) |
| Boîtier | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | UV erasure + parallel programmer |
| Process Technology | CMOS, UV-erasable floating gate |
| Type de montage | Through-hole |
Configuration des broches de EP610DC-20
| Broche 1 | I/O0 — Bidirectional I/O pin 0 (macrocell 0) |
| Broche 2 | I/O1 — Bidirectional I/O pin 1 (macrocell 1) |
| Broche 3 | I/O2 — Bidirectional I/O pin 2 (macrocell 2) |
| Broche 4 | I/O3 — Bidirectional I/O pin 3 (macrocell 3) |
| Broche 5 | I/O4 — Bidirectional I/O pin 4 (macrocell 4) |
| Broche 6 | I/O5 — Bidirectional I/O pin 5 (macrocell 5) |
| Broche 7 | I/O6 — Bidirectional I/O pin 6 (macrocell 6) |
| Broche 8 | I/O7 — Bidirectional I/O pin 7 (macrocell 7) |
| Broche 9 | GND — Ground |
| Broche 10 | INPUT0 — Dedicated input 0 |
| Broche 11 | I/O8 — Bidirectional I/O pin 8 (macrocell 8) |
| Broche 12 | I/O9 — Bidirectional I/O pin 9 (macrocell 9) |
| Broche 13 | I/O10 — Bidirectional I/O pin 10 (macrocell 10) |
| Broche 14 | I/O11 — Bidirectional I/O pin 11 (macrocell 11) |
| Broche 15 | I/O12 — Bidirectional I/O pin 12 (macrocell 12) |
| Broche 16 | I/O13 — Bidirectional I/O pin 13 (macrocell 13) |
| Broche 17 | I/O14 — Bidirectional I/O pin 14 (macrocell 14) |
| Broche 18 | I/O15 — Bidirectional I/O pin 15 (macrocell 15) |
| Broche 19 | INPUT1 — Dedicated input 1 |
| Broche 20 | INPUT2 — Dedicated input 2 |
| Broche 21 | INPUT3 — Dedicated input 3 |
| Broche 22 | CLK/CLR — Clock/Clear (per datasheet pinout; verify in device programmer) |
| Broche 23 | VCC — +5 V supply |
| Broche 24 | VCC — +5 V supply (second VCC pin) |
Applications typiques
EP610DC-20 convient pour 6 applications: Legacy Bus Address Decoding, State Machine Controllers, Register and Counter Arrays, Industrial Control Logic Replacement, Military and Aerospace Legacy Support, Retrocomputer and Hobbyist Projects.
Legacy Bus Address Decoding
The EP610DC-20's 22 ns propagation delay and 16 bidirectional I/O pins make it well-suited for replacing multiple 74LS/74F-series address-decoder packages in legacy ISA, VME, or STD-bus cards. With 160 product terms and 16 macrocells, the device can decode a 16-bit address space and generate multiple chip-select outputs in a single package, reducing board area by 3-5x compared to discrete TTL. The 5 V single-supply operation matches the bus voltage directly, eliminating level translators. Compared to discrete gates, the EP610DC-20 offers deterministic tPD across all paths because the AND-OR-NOT architecture uses a fixed product-term array. For new designs, MAX II CPLDs provide more capacity, but the EP610DC-20 remains a drop-in solution for maintaining 1990s-era industrial controllers.
Recommandé
State Machine Controllers
The EP610DC-20's 16 macrocells with configurable D/T/JK flip-flops and 22 ns tPD support multi-state FSMs (Mealy or Moore) up to 16 states with combinational outputs. Each macrocell provides a programmable polarity output and tri-state control, allowing the designer to implement both registered and combinational logic in one device without external glue logic. The 55.6 MHz fMAX makes the device suitable for sequencing control loops in industrial machinery running at clock rates up to several MHz. The 160 product terms comfortably handle 10-state controllers with 4-input state-decoding logic. Engineers should use Altera MAX+PLUS II for FSM synthesis with safe state encoding (Gray or one-hot) to minimize product-term usage.
Recommandé
Register and Counter Arrays
The EP610DC-20's 16 macrocells can implement up to 16 flip-flops (D, T, JK, or latch), allowing designers to replace 4 to 5 packages of 74LS/74F register or counter logic with a single PLD. With a 55.6 MHz maximum toggle frequency and 22 ns tPD, the device supports synchronous counters and shift registers running at clock rates up to approximately 25 MHz. The 5 V single-supply operation directly interfaces with TTL logic without level translation. Compared to discrete 74LS counters, the EP610DC-20 reduces power consumption by 50-70% and PCB area by 80%. Engineers should allocate one macrocell per flip-flop and use the dedicated clock/clear pins for synchronous resets.
Recommandé
Industrial Control Logic Replacement
The EP610DC-20's ceramic CDIP-24 package with UV window and 5 V supply operation make it a robust choice for industrial control retrofits where the original Altera Classic design must be replicated. With 16 macrocells and 160 product terms, the device handles medium-complexity sequencing, interlocks, and I/O expansion for PLC cards, motor controllers, and SCADA interfaces. The 0 °C to 70 °C commercial temperature range covers most factory-floor environments when mounted inside an enclosure. The 22 ns tPD ensures deterministic response time for safety-critical interlocks. Engineers should verify lot date codes and request MIL-STD-883 screening for high-reliability industrial applications.
Recommandé
Military and Aerospace Legacy Support
The EP610DC-20's 24-pin ceramic DIP package with UV-erasable window is uniquely suited to long-life military and aerospace programs that require a hermetic, leaded, electrically-programmable logic device. With 22 ns tPD and 16 macrocells, the device provides glue-logic functionality for legacy avionic, missile, and naval systems originally designed in the 1980s and 1990s. The UV-clearable configuration allows program updates and security erase in the field without specialized EEPROM programmers. Franchised distributors such as Rochester Electronics maintain inventory of date-coded EP610DC-20 stock for these programs. For new designs, engineers should migrate to modern QML-qualified FPGAs.
Recommandé
Retrocomputer and Hobbyist Projects
The EP610DC-20's UV-erasable CMOS design, 24-pin DIP footprint, and through-hole mounting make it a popular choice for retrocomputing hobbyists building replicas of 1980s-era computers, arcade boards, and vintage synthesizer controllers. With 16 macrocells, the device can implement address decoders, video timing generators, and I/O expanders for systems such as Z80, 6502, or 68K retrocomputers. The 22 ns tPD matches the timing requirements of vintage 8-bit and 16-bit CPUs. The CDIP-24 socket-friendly package simplifies prototyping on breadboards and perfboards. Hobbyists should pair the EP610DC-20 with a TL866 II Plus or comparable EPROM/PLD programmer that supports the Altera Classic device family.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP610DC-20 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP610DC-15 | EP610DC-10 | EP610DC-25 | EP610PC-20 | EP610LC-20 | EP610DC-30 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | CDIP-24 | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same |
| Propagation Delay (tPD) | 22 ns | 15 ns (-32%) | 10 ns (-55%) | 25 ns (+14%) | 22 ns (same) | 22 ns (same) | 30 ns (+36%) |
| Logic Macrocells | 16 | 16 (same) | 16 (same) | 16 (same) | 16 (same) | 16 (same) | 16 (same) |
| Product Terms | 160 | 160 (same) | 160 (same) | 160 (same) | 160 (same) | 160 (same) | 160 (same) |
| fMAX | 55.6 MHz | 55.6 MHz (same) | 55.6 MHz (same) | 55.6 MHz (same) | 55.6 MHz (same) | 55.6 MHz (same) | 55.6 MHz (same) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V (low-power) | 5 V |
| Operating Temperature | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Lowest cost in the EP610 Classic speed-grade family (vs EP610DC-15)
- Ceramic CDIP-24 package with UV window for field erasure (vs EPM3064ATC44-10 (MAX 3000A))
- Pin-compatible with entire EP610 speed-grade family (vs EPM240T100C5N (MAX II))
Notes de conception
The EP610DC-20 requires 0.1 µF ceramic decoupling capacitors placed within 5 mm of each VCC pin (pins 23 and 24), plus a 10 µF tantalum bulk capacitor on the board-level 5 V rail. The CDIP-24 package has two VCC pins that MUST both be connected; leaving either floating can cause intermittent logic errors. According to the Altera EP610 datasheet, the supply tolerance is ±5% (4.75 V to 5.25 V), so a regulated 5 V rail is required rather than an unregulated 5 V from a linear transformer. Designers migrating to faster speed grades (DC-15, DC-10) should re-measure decoupling margins because ICC increases slightly with switching frequency.
The ceramic DIP-24 socket must support UV-erase access - use a low-profile open-frame socket (e.g., 3M 224-1285-00-0602J) that leaves the quartz window exposed. Closed-frame sockets will physically block UV erasure. Place the EP610DC-20 away from heat-generating components; the ceramic package is hermetic but does not dissipate heat as well as modern leadless packages. For socketed programming, route all programming signals (DATA, CLK, OE) to a 10-pin JTAG-style header to allow in-system programming without removing the device. Verify pin 1 orientation - the UV window is on the same side as the notch in a standard DIP.
Estimated: at fMAX = 55.6 MHz and VCC = 5.25 V, ICC is approximately 200-300 mA depending on output loading; verify with a scope before declaring the power budget closed. Do not program the EP610DC-20 with a JEDEC file generated for the EP610DC-15 or EP610DC-10 unless the silicon speed grade supports it - faster-grade files will work in slower-grade silicon, but slower-grade files may violate timing in faster-grade silicon. Never program the device while it is soldered into a powered circuit; isolate VCC and disconnect the 5 V rail during programming. Finally, do not mix CDIP and PDIP packages on the same board - the pinout is identical but the UV window behavior differs.
Informations de conformité
EP610DC-20 predates the RoHS directive; compliance depends on the specific lot date code and distributor re-screening. AEC-Q100 not applicable for legacy programmable logic. Engineers should request a compliance certificate from the distributor before placing production orders.
