EP610DC-35 vs EP610DC35 Comparaison
Comparaison détaillée côte à côte de EP610DC-35 par Altera et EP610DC35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610DC-35 | EP610DC35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,40 | $19,20 |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | Classic EPLD |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Boîtier | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| Type de montage | Through-Hole (DIP) | Through-Hole |
| Température de fonctionnement | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | [DATA_NEEDED: operating temperature range] |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| Statut RoHS | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Maximum Frequency | — | 28.6 MHz |
| Tension d'alimentation | — | 5 V |
| Nombre de broches | — | 24 |
| Technology | — | UV-erasable CMOS EPROM |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |