EP610DC-35 vs EP610DC35 비교
다음의 상세 나란히 비교: EP610DC-35 제조: Altera 및 EP610DC35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610DC-35 | EP610DC35 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $18.40 | $19.20 |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | Classic EPLD |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| 패키지 | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| 실장 유형 | Through-Hole (DIP) | Through-Hole |
| 동작 온도 | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | [DATA_NEEDED: operating temperature range] |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| RoHS 상태 | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Maximum Frequency | — | 28.6 MHz |
| 공급 전압 | — | 5 V |
| 핀 수 | — | 24 |
| Technology | — | UV-erasable CMOS EPROM |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |