EP910ILC-25 vs EP910IDC-15 Comparaison
Comparaison détaillée côte à côte de EP910ILC-25 par Intel et EP910IDC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910ILC-25 | EP910IDC-15 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $9,95 |
| Family | EP910 Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Boîtier | 44-pin JLCC (windowed ceramic) | 40-pin CDIP (Ceramic DIP, through-hole) |
| Type de montage | Surface Mount | — |
| Température de fonctionnement | -40C to +85C (industrial) | — |
| Tension d'alimentation | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Statut RoHS | non_compliant (ceramic windowed package) | non_compliant (ceramic DIP contains lead) |
| Statut du cycle de vie | Obsolete - last time buy was late 1990s | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Dedicated Inputs | — | 10 |
| Programming Technology | — | EPROM (UV-erasable) |