EP910ILC-25 vs EP910IDC-15 比較
詳細な並列比較: EP910ILC-25 メーカー: Intel および EP910IDC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910ILC-25 | EP910IDC-15 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $9.95 |
| Family | EP910 Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| パッケージ | 44-pin JLCC (windowed ceramic) | 40-pin CDIP (Ceramic DIP, through-hole) |
| 実装タイプ | Surface Mount | — |
| 動作温度 | -40C to +85C (industrial) | — |
| 電源電圧 | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS ステータス | non_compliant (ceramic windowed package) | non_compliant (ceramic DIP contains lead) |
| ライフサイクル状態 | Obsolete - last time buy was late 1990s | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Dedicated Inputs | — | 10 |
| Programming Technology | — | EPROM (UV-erasable) |