EP910IPC-25 vs EP910IPC-50 Comparaison
Comparaison détaillée côte à côte de EP910IPC-25 par Intel et EP910IPC-50 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910IPC-25 | EP910IPC-50 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,40 | $13,85 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | — |
| Usable Gates | 450 | — |
| Macrocells | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 25 ns | 50 ns |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Température de fonctionnement | 0C to +70C (commercial grade) | -40C to +85C (industrial) |
| Boîtier | 40-pin PDIP (PDIP-40) | 40-pin Ceramic DIP (IPC, windowed) |
| Type de montage | Through-Hole | Through-Hole (DIP) |
| Programming Method | EPROM cell (OTP / UV erasable) | Off-board EPROM programmer + UV erase |
| Development Tool | MAX+PLUS II | — |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Technology | — | CMOS EPROM cell |
| Erasure Method | — | UV light through ceramic window (IPC package) |
| Statut RoHS | — | [DATA_NEEDED: not stated in verified data] |