EP910IPC-25 vs EP910IPC-50 比較
詳細な並列比較: EP910IPC-25 メーカー: Intel および EP910IPC-50 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910IPC-25 | EP910IPC-50 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $13.85 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | — |
| Usable Gates | 450 | — |
| Macrocells | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 25 ns | 50 ns |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| 動作温度 | 0C to +70C (commercial grade) | -40C to +85C (industrial) |
| パッケージ | 40-pin PDIP (PDIP-40) | 40-pin Ceramic DIP (IPC, windowed) |
| 実装タイプ | Through-Hole | Through-Hole (DIP) |
| Programming Method | EPROM cell (OTP / UV erasable) | Off-board EPROM programmer + UV erase |
| Development Tool | MAX+PLUS II | — |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Technology | — | CMOS EPROM cell |
| Erasure Method | — | UV light through ceramic window (IPC package) |
| RoHS ステータス | — | [DATA_NEEDED: not stated in verified data] |