EP910JC-30 vs EP910LC-30 Comparaison
Comparaison détaillée côte à côte de EP910JC-30 par Intel et EP910LC-30 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910JC-30 | EP910LC-30 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $22,50 |
| Family | Classic EPLD (MAX-style) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | — |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | — |
| Boîtier | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| Type de montage | Surface Mount (socket-mountable) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | — | 24 |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Maximum Toggle Frequency | — | 62 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal, TTL) |
| Process Technology | — | CMOS (EPROM-based) |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Programming Technology | — | UV-erasable EPROM cell |
| Development Tool | — | Altera MAX+PLUS II |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |