EP910LC44-30T vs EP910LC44 Comparaison
Comparaison détaillée côte à côte de EP910LC44-30T par Altera et EP910LC44 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP910LC44-30T | EP910LC44 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $8,95 |
| Device Family | Classic EPLD | — |
| Logic Type | PAL-type CMOS EPLD (OT PLD) | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 33 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | 12 | 12 |
| I/O Lines | 24 (bidirectional) | — |
| Total Inputs | 36 | — |
| Total Outputs | 24 | — |
| External Clock Inputs | 2 | — |
| Programming Technology | CMOS, UV-erasable (windowed package in family) | — |
| Security Bit | Programmable (logic readback protection) | — |
| Operating Temperature Grade | Commercial | — |
| Boîtier | PQCC-44 (Plastic Leaded Chip Carrier, J-bend) | 44-pin PLCC (J-leaded) |
| Terminal Form | J-BEND | — |
| Package Code | QCCJ | — |
| Type de montage | Surface Mount | — |
| Product Family | — | Classic EPLD (EP910 Series) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Input Pins | — | 36 (12 dedicated + 24 I/O as inputs) |
| Global Clock Inputs | — | 2 |
| Propagation Delay (LC grade) | — | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | — | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | — | CMOS |
| Température de fonctionnement | — | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Programming Method | — | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| Architecture | — | AND-OR sum-of-products with programmable macrocell feedback |
| Logic Compatibility | — | TTL-compatible CMOS I/O |
| Statut RoHS | — | [DATA_NEEDED: not stated in verified data] |