EPC1441LC20N vs EPC1441LI20 Comparaison
Comparaison détaillée côte à côte de EPC1441LC20N par Intel et EPC1441LI20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1441LC20N | EPC1441LI20 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,95 | $8,10 |
| Type de mémoire | OTP EPROM (One-Time Programmable) | OTP Configuration PROM (PROM) |
| Taille de mémoire | 440 Kbit | — |
| Organisation de la mémoire | 55 K x 8 bit | — |
| Interface | Serial, 4-wire (nCS, DCLK, DATA, nINIT_CONF) | — |
| Configuration Clock (DCLK) | 8 MHz maximum | — |
| Programming Interface | JTAG (IEEE 1149.1) / Altera Programming Unit | — |
| Tension d'alimentation | 3.3 V (typical) | 3.3 V |
| Boîtier | 20-PLCC (J-Lead, 9 x 9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Température de fonctionnement | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Cascadable | Yes (nCS daisy-chain) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Type de montage | Surface Mount (PLCC socket compatible) | — |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Configuration Interface | — | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Pin Pitch | — | 1.27 mm |
| Programming Method | — | One-Time-Programmable via Altera programming hardware |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |