EPC16UC88 vs EPC16UI88AA Comparaison
Comparaison détaillée côte à côte de EPC16UC88 par Altera et EPC16UI88AA par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16UC88 | EPC16UI88AA |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Unknown | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $15,65 |
| Device Type | In-system programmable configuration PROM for FPGAs | — |
| Configuration Memory Capacity | 16 Mb | — |
| Tension d'alimentation | 3.3 V core and I/O | — |
| Boîtier | 88-UBGA (11x8) | 88-ball UBGA |
| Package Family | UBGA | — |
| In-System Programmability | IEEE Std. 1532 compatible | — |
| Programming Language Support | Jam Standard Test and Programming Language (STAPL) | — |
| JTAG Boundary Scan | Supported | — |
| nINIT_CONF Function | Allows private JTAG instruction to start FPGA configuration | — |
| Configuration Architecture | Configuration controller and flash memory | — |
| FPGA Configuration Use | Automatic configuration after power-up or system initialization | — |
| Data Output | Configuration data output controlled by OE and nCS | — |
| Output Control | OE and nCS control tri-state buffer and address counter | — |
| Type de montage | Surface mount | Surface Mount |
| Package Dimensions | 11 mm x 8 mm | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature] | [DATA_NEEDED: operating temperature range] |
| Output Current | [DATA_NEEDED: output current] | — |
| Configuration Frequency | [DATA_NEEDED: configuration frequency] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Type de mémoire | — | NOR Flash (Enhanced Configuration Device) |
| Taille de mémoire | — | 16 Mbit |
| Memory Organization | — | 16M x 1 bit |
| Type d'interface | — | Serial FPGA Configuration Bus + JTAG |
| Configuration Clock Frequency | — | 66.7 MHz (max) |
| Supply Voltage (VCC) | — | 3.3 V |
| Output Characteristics | — | 3-STATE |
| Write/Erase Endurance | — | 100,000 cycles |
| Programming Method | — | In-system via JTAG |
| Multi-Page Boot Support | — | Yes (multiple bitstream images) |
| Family | — | Enhanced Configuration Device (EPC4/EPC8/EPC16) |