EPC18QI100 vs EPC8QI100 Comparaison
Comparaison détaillée côte à côte de EPC18QI100 par Altera et EPC8QI100 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC18QI100 | EPC8QI100 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,40 | $10,85 |
| Manufacturer | Altera (now Intel Programmable Solutions Group) | — |
| Device Type | FPGA Configuration PROM (nonvolatile) | — |
| Memory Density | 18 Mbit (18,874,368 bits) | — |
| Configuration Interface | Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V tolerant | — |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| Cascading Support | Yes (via nCASC pin, multi-device chains supported) | — |
| Boîtier | 100-pin PQFP (Plastic Quad Flat Pack) | 100-PQFP (20 x 14 mm) |
| Package Dimensions | 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads) | — |
| Plage de température de fonctionnement | -40 C to +85 C (industrial) | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Lead Finish | Matte tin (lead-free, per Altera Pb-free roadmap) | — |
| Statut RoHS | Compliant (Pb-free part marking) | Non-compliant (legacy PQFP, lead-bearing) |
| Configuration Time | [DATA_NEEDED: configuration time at typical DCLK] | — |
| End-of-Life Status | Obsolete; replaced by Altera/Intel EPCQ family | — |
| Type de mémoire | — | Flash (NOR, Enhanced Configuration PROM) |
| Taille de mémoire | — | 8 Mbit |
| Supply Voltage (Core) | — | 3.3 V |
| Supply Voltage (I/O) | — | 3.3 V |
| Interface | — | Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) |
| In-System Programmability | — | IEEE Std. 1532 compliant |
| Programming Language | — | Jam STAPL |
| Boundary Scan | — | JTAG boundary-scan test supported |
| Data Compression | — | Yes (increases effective capacity) |
| Configuration Controller | — | On-chip, dedicated to Altera FPGAs |
| Initiate-Configuration Pin | — | nINIT_CONF (private JTAG instruction) |
| Température de fonctionnement | — | -40C to +85C (industrial) |
| Compatible FPGAs | — | Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX |